Circuit techniques for reducing the minimum supply voltage (VMIN) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (VMAX) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache VMINwhile simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a VMINreduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache VMINwith SECDED. Therefore, SECDED improves VMINby 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.

Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multitasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low voltage data-retention failure mechanism in flops. It analyzes the impact of design and process parameters on the data retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. In this paper, we propose a new architecture that significantly reduces the array switching power for SRAM. The proposed architecture combines built-in self-test and digitally controlled delay elements to reduce the wordline pulsewidth for memories while ensuring correct read operations, hence reducing the switching power. Monte Carlo simulations using a 1-Mb SRAM macro in an industrial 45-nm technology are used to verify the power saving for the proposed architecture. For a 48-Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it an attractive solution for 45-nm-and-below technologies.

The increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. This is aggravated by the strong demand for lower cost and power consumption, higher performance and density which complicates SRAM design process. In this paper, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow enables early SRAM yield predication and performance/power optimization in the design time, which is important for SRAM in nanometer technologies. The methodology is verified using measured silicon yield data from a 1 Mb memory fabricated in an industrial 45nm technology.