Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Dipak Sitaram

dblp:43/2103 · DBLP profile ↗
← Back
4ranked-venue papers
3as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › signal integrity
crosstalk analysis
0.012004
Full-chip, three-dimensional shapes-based RLC extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation › physical design
parasitic extraction
0.012004
Full-chip, three-dimensional shapes-based RLC extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation
signal integrity
0.012004
Full-chip, three-dimensional shapes-based RLC extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation › interconnect modeling
inductance extraction
0.012004
Full-chip, three-dimensional shapes-based RLC extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004
Electronic design automation
interconnect modeling
0.012004
Full-chip, three-dimensional shapes-based RLC extraction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2004

Methods — techniques the papers use, named apart from their topics

return-limited inductance · 0.0finite element method · 0.0
YearPublicationVenuePosition
2004 Full-chip, three-dimensional shapes-based RLC extraction
abstract
In this paper, we report the development of a full-chip, three-dimensional, shapes-based, resistence-inductance-capacitance extraction tool, which was developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate crosstalk analysis. The tool exploits high-capacity scan-band techniques and disk caching. Accuracy is validated by comparison with full-wave finite-element field solvers.
Dipak Sitaram, Kenneth L. Shepard
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2002 Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
abstract
Full-wave analysis, based on rigorous solution of the differential or integral form of Maxwell's equations, is too slow for all but the smallest designs. Traditional on-chip extraction engines are, therefore, being pushed to extract inductance and provide accurate high-frequency interconnect modelling while maintaining computational efficiency and capacity. This paper describes further accuracy-improving enhancements to the commecial full-chip RLCK extraction engine, Assura RLCX[1], based on the return-limited inductance formulation. Specifically, we incorporate substrate losses due to eddy currents and power-ground losses while, based on design-driven assumptions, avoiding explicit extraction of the power-ground and substrate. Results are validated on small testcases where comparison with full-wave solution is practical.
Dipak Sitaram, Kenneth L. Shepard
ICCAD1
2000 Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction
abstract
In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor.
Kenneth L. Shepard, Dipak Sitaram
ICCAD2
1991 A Random Distributed Algorithm to Embed Trees in Partially Faulty Processor Arrays
Dipak Sitaram, Israel Koren, C. Mani Krishna 0001
J. Parallel Distributed Comput.1