The various requirements in terms of data rates and latency in beyond 5G and 6G networks have motivated the integration of a variety of communications schemes and technologies to meet these requirements in such networks. Among these schemes are Terahertz (THz) communications, cooperative non-orthogonal multiple-access (NOMA)-enabled schemes, and mobile edge computing (MEC). THz communications offer abundant bandwidth for high-data-rate short-distance applications and NOMA-enabled schemes are promising schemes to realize the target spectral efficiencies and low latency requirements in future networks, while MEC would allow distributed processing and data offloading for the emerging applications in these networks. In this paper, an energy-efficient scheme of multi-user NOMA-assisted cooperative THz single-input multiple-output (SIMO) MEC systems is proposed to allow the uplink transmission of offloaded data from the far cell-edge users to the more computing resources in the base station (BS) through the cell-center users. To reinforce the performance of the proposed scheme, two optimization problems are formulated and solved, namely, the first problem minimizes the total users’ energy consumption while the second problem maximizes the total users’ computation energy efficiency (CEE) for the proposed scheme. In both problems, the NOMA user pairing, the BS receive beamforming, the transmission time allocation, and the NOMA transmission power allocation coefficients are optimized, while taking into account the full-offloading requirements of each user as well as the predefined latency constraint of the system. The obtained results reveal new insights into the performance and design of multi-user NOMA-assisted cooperative THz-SIMO MEC systems. Particularly, with relatively high offloading rate demands (several Gbits/user), we show that (i) the proposed scheme can handle such demands while satisfying the predefined latency constraint, and (ii) the full-offloading model can be considered the most effective solution in conserving mobile devices’ resources as compared to the system with the partial-offloading model or the system without offloading.

Abstract This work proposed a new metaheuristic dubbed as Chaotic Lévy flight distribution (CLFD) algorithm, to address physical world engineering optimization problems that incorporate the chaotic maps in the elementary Lévy flight distribution (LFD). Hybridization aims to increase the LFD rate of convergence while also providing a problem‐free optimization approach. The proposed methodology is investigated for five case studies of constrained optimization issues followed by shape optimization of structural design. The outcomes from the CFLD algorithm are further contrasted with its fundamental version and other distinguished recently introduced algorithms. The computational analysis illustrates the dominance of CLFD over other considered optimizers. Moreover, the present investigation shows that CLFD is a robust technique that can efficiently find optimal mechanical design problems with a proper chaotic map selection.

Terahertz (THz) communication is gaining more interest as one of the envisioned enablers of high-data-rate short-distance indoor applications in beyond 5G networks. Moreover, non-orthogonal multiple-access (NOMA)-enabled schemes are promising schemes to realize the target spectral efficiency, low latency, and user fairness requirements in future networks. In this paper, an energy-efficient cooperative NOMA (CNOMA) scheme that guarantees the minimum required rate for the cell-edge users in an indoor THz-MISO communications network is proposed. The proposed cooperative scheme consists of three stages: (i) beamforming stage that allocates base-station (BS) beams to THz cooperating cell-center users using analog beamforming with the aid of the cosine similarity metric, (ii) user pairing stage that is tackled using the Hungarian algorithm, and (iii) power allocation stage for both the BS THz-NOMA transmit power and the cooperation power of the cooperating cell-center users, which are optimized sequentially. The obtained results quantify the energy efficiency (EE) of the proposed scheme and shed new light on the performance of multi-user THz-NOMA-enabled networks.

Abstract Structural design and optimization are important topics for the control and design of industrial robots. The motivation behind this research is to design a robot gripper mechanism. To explore robust design of the robot gripper mechanism, a new optimization approach based on a grasshopper optimization algorithm and Nelder–Mead algorithm is developed for requiring a fast and accurate solution. Additionally, a vehicle side crash design problem, a multi‐clutch disc problem, and a manufacturing optimization problem are solved with the developed method to show the advantages of the new technique (HGOANM). Both engineering comparisons and production problem results in which HGOANM is applied are compared with the latest optimization techniques in the literature. The results of the problems resolved in this article reveal that the developed HGOANM is an essential optimization approach by solving real‐world engineering problems quickly and accurately.

In this paper, we investigate simultaneous lightwave information and power transfer (SLIPT) for underwater visible light communication systems. We consider three SLIPT methods namely time switching (TS), power splitting (PS) and time switching-power splitting (TS-PS) where the splitting/switching factors are defined as optimization parameters. For each of these methods, we derive closed-form expressions for the average harvested energy, bit error rate and spectral efficiency in the presence of underwater turbulence modeled by lognormal statistics. Using these expressions, we determine the optimal splitting factors to maximize the harvested energy while satisfying a given bit error rate value and a given threshold spectral efficiency value. Our results reveal that, if not optimized, SLIPT methods under consideration are outperformed by the simple AC-DC separation (ADS) method which provides the largest harvested energy versus spectral efficiency (HE-SE) region. Optimization of splitting/switching factors extends the HE-SE regions; hence, optimized versions of TS, PS and TS-PS methods are able to significantly outperform ADS for most cases. We further investigate the effect of various channel and system parameters such as water type, turbulence level, beam divergence, receiver aperture size on the harvested energy and quantify the improvements in battery lifetime through the use of SLIPT methods.

With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and protecting sensitive transistors, whose soft error detection probability is relatively high, until desired circuit reliability is achieved or a given area overhead constraint is met. Transistors are protected based on duplicating and sizing a subset of transistors necessary for providing the protection. In addition to that, a novel gate-level reliability evaluation technique is proposed that provides similar results to reliability evaluation at the transistor level (using SPICE) with the orders of magnitude reduction in CPU time. LGSynth'91 benchmark circuits are used to evaluate the proposed algorithm. Simulation results show that the proposed algorithm achieves better reliability than other transistor sizing-based techniques and the triple modular redundancy technique with significantly lower area overhead for 130-nm process technology at a ground level.

Up to writing this paper, existing High Performance Computing (HPC) systems do not provide proper quality of service (QoS) controls and reliability features because of two limitations: first, standard middleware libraries such as Message Passing Interface (MPI) and Parallel Virtual Machine (PVM) do not provide means for applications to specify service quality for computation and communication. Second, modern high-speed interconnects such as Infiniband, Myrinet and Quadrics are optimized for performance rather than fault-tolerance and QoS control. The Data-Centric Publish-Subscribe (DCPS) model - the core of Data Distribution Service (DDS) systems - defines standards that enable applications running on heterogeneous platforms to control various QoS policies in a net-centric system. In this paper, we present our novel model of incorporating DDS QoS and reliability controls into HPC systems. Our results show that DDS integration into HPC adds considerable overheard in terms of performance and network utilization, when the application is mainly communication.

Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flexibility and high fabrication yield advantages of CMOS technology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nano-wires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and overcomes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like connectivity domain, reduces the flexibility of VLSI design automation and further complicates cells placement.

Route optimization (RO) is an important feature of the Electric Vehicles (EVs) which is responsible for finding optimized paths between any source and destination nodes in the road network. In this paper, the RO problem of EVs is solved by using the Multi Constrained Optimal Path (MCOP) approach. The proposed MCOP problem aims to minimize the length of the path and meets constraints on total travelling time, total time delay due to signals, total recharging time, and total recharging cost. The Penalty Function method is used to transform the MCOP problem into unconstrained optimization problem. The unconstrained optimization is performed by using a Particle Swarm Optimization (PSO) based algorithm. The proposed algorithm has innovative methods for finding the velocity of the particles and updating their positions. The performance of the proposed algorithm is compared with two previous heuristics: H_MCOP and Genetic Algorithm (GA). The time of optimization is varied between 1 second (s) and 5s. The proposed algorithm has obtained the minimum value of the objective function in at-least 9.375% more test instances than the GA and H_MCOP.

The look-up table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to parallelize the LUT method so that more pixels can be concurrently inverse halftoned using minimum additional hardware. The proposed algorithm partitions the single LUT of serial LUT method into N smaller look-up tables (s-LUTs) such that the total number of entries in all s-LUTs remain equal to the number of entries in the single LUT of serial LUT method. The proposed algorithm can be implemented on a single FPGA (field programmable gate arrays) device with external memories to store s-LUTs.

The paper discusses the parallelization of stochastic evolution metaheuristic, identifying effective parallelization for a distributed parallel environment. Multiobjective VLSI cell placement is used as an optimization problem. A comprehensive set of parallelization approaches are tested and an effective strategy is identified in terms of two underlying factors: workload division and the effect of parallelization on metaheuristic's search intelligence. The strategies are compared with parallelization of another similar evolutionary metaheuristic called simulated evolution. The role of the two mentioned underlying factors is discussed in parallelization of stochastic evolution, the parallelized version of which has not been presented before.

Simulated evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to well established stochastic heuristics such as SA, TS and GA, with shorter runtimes. However, for problems with a very large set of elements to optimize, such as in VLSI placement and routing, runtimes can still be very large and parallelization is an attractive option. Compared to other metaheuristics, parallelization of SimE has not been extensively explored. This paper presents a comprehensive set of parallelization approaches for SimE when applied to multiobjective VLSI cell placement problem. Each of these approaches are evaluated with respect to SimE characteristics and the constraints imposed by the problem instance. Conclusions drawn can be extended to parallelization of other SimE based optimization problems

In this paper, we address the problem of FSM state assignment to minimize area and power. The objectives are targeted as single/independent as well as multi-objective optimization (MOP) problems. Methods for estimating area and power of an FSM are presented. A fuzzy-based aggregation function is employed to combine the two objectives. The work employs genetic algorithm for search space exploration. Experimental results demonstrate the effectiveness of the proposed measures.

Simulated annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinatorial optimization problems. However, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up its execution is to parallelize it. In this paper we develop parallel SA schemes based on the asynchronous multiple-Markov chain model (AMMC) described in S.-Y. Lee and K. G. Lee (1996) and applied to standard-cell placement as presented in J. Chandy et al. (1997), The schemes are applied to solve the multi-objective standard cell placement problem using an inexpensive cluster-of-workstations environment. This problem requires the optimization of conflicting objectives (interconnect wire-length, power dissipation, and timing performance), and fuzzy logic is used to integrate the costs of these objectives stated in J.A. Khan et al. (2002) and S. M. Sait and H. Youssef (2001). Experiments are performed on ISCAS-85/89 benchmark circuits. Our goal is to develop parallel SA schemes that provide significantly improved runtime/solution quality characteristics for this key CAD problem, by making the best possible use of an inexpensive parallel environment.

Designing and planning of the switching, signaling and support network is a fairly complex process in cellular mobile network. In this paper, the problem of assigning cells to switches in cellular mobile network, which is considered a planning problem, is addressed. The cell to switch assignment problem which falls under the category of the Quadratic Assignment Problem (QAP) is a proven NP--hard problem. Further, the problem is modeled to include an additional constraint in the formulation. The additional constraint is of the maximum number of switch ports that are used for a cell's Base Station Transceiver System (BTS) connectivity to the switch. The addition of the constraint on the number of ports on a switch has immense practical significance. This paper presents a non--deterministic heuristic based on Simulated Evolution (SimE) iterative algorithm to provide solutions. The methods adopted in this paper are a completely innovative formulation of the problem and involve application of Evolutionary Computing for this complex problem that may be extended to solutions of similar problems in VLSI design, distributed computing and many other applications.

Open Shortest Path First (OSPF) is a routing protocol which is widely used in the Industry. Its functionality mainly depends on the weights assigned to the links. Given the traffic demands on a network, setting weights such that congestion can be avoided is an NP-hard problem. Optimizing these link weights leads to efficient network utilization which is the main goal of traffic engineering. In this paper, Simulated Annealing iterative heuristic is applied to this problem. This will provide close-to-optimal solutions that can be used for network provisioning. For this problem, the cost function that has been used in the literature depends solely on the links utilization and therefore optimizes only the network utilization. In this paper, our goal is to optimize the number of congested links in the network in addition to the utilization. Therefore, we propose a new cost function that depends on the utilization and the extra load caused by congested links in the network. This provides the network designer with more flexibility to optimize desired parameters. Our results show less number of congested links and comparable extra load in the network when compared to results of using the existing cost function.

The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques

In this paper we present efficient Reverse Order Restoration (ROR) based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation based restoration of test subsequences, our technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using State Traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques.

Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with significant run times. Two parallel models for GA are presented for VLSI cell placement where the objectives are optimizing power dissipation, timing performance and interconnect wirelength, while layout width is a constraint. A Master-Slave approach is mentioned wherein both fitness calculation and crossover mechanism are distributed among slaves. A Multi-Deme parallel GA is also presented in which each processor works independently on an allocated subpopulation followed by information exchange through migration of chromosomes. A pseudo-diversity approach is taken, wherein similar solutions with the same overall cost values are not permitted in the population at any given time. A series of experiments are performed on ISCAS-85/89 benchmarks to show the performance of the Multi-Deme approach.

In this paper we present an evaluation of selected parallel strategies for Simulated Annealing and Simulated Evolution, identifying the impact of various issues on the effectiveness of parallelization. Issues under consideration are the characteristics of these algorithms, the problem instance, and the implementation environment. Observations are presented regarding the impact of parallel strategies on runtime and achievable solution quality. Effective parallel algorithm design choices are identified, along with pitfalls to avoid. We further attempt to generalize our assessments to other heuristics.

Evolutionary algorithms have been studied by several researchers for the design of digital circuits. Simulated evolution (SimE) is used in This work due to it simplicity and customizability to combinatorial problems. A tree data structure based circuits are evolved. Thus, a larger solution space is investigated. In addition, a new pattern based goodness measure is presented.

With the increasing demand for high quality, more efficient, less area and less power circuits, the problem of logic circuit design has become a multiobjective optimization problem. Multiobjective optimization of logic circuits based on a fuzzified ant colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power for some known circuits. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS.

Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biological organisms. The new paradigm is expected to radically change the synthesis procedures in a way that can help discovering novel designs and/or more efficient circuits. In this paper, a multiobjective optimization of logic circuits based on a modified ant colony (ACO) algorithm is presented. The performance of the proposed algorithm is evaluated using a set of randomly generated circuits. The results obtained using the proposed algorithm are compared to those obtained using existing ACO-based techniques. It is shown that the designed circuits using the proposed algorithm outperform those of the existing techniques.

In this paper, the use of simulated evolution (SimE) algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorithm are compared to those obtained by genetic algorithm (GA).

Parallelizing any algorithm on a cluster of heterogeneous workstations is not easy, as each workstation requires different wall clock time to execute the same instruction set. In this work, a parallel tabu search algorithm for heterogeneous workstations is presented using PVM. Two parallelization strategies, i.e., functional decomposition and multi-search thread strategies are integrated. The proposed algorithm is tested on the VLSI standard cell placement problem, however, the same algorithm can be used on any combinatorial optimization problem. The results are compared ignoring heterogeneity and are found to be superior in terms of execution time.

In each iteration of a simulated evolution (SE) algorithm for VLSI placement, poorly placed cells are selected probabilistically, based on a measure known as 'goodness'. To compensate for the error in the goodness calculation (and to maintain the number of selected cells within some limit), a parameter known as 'bias' is used, which has major impact on the algorithm's run-time and on the quality of the solution subspace searched. However, it is difficult to select the appropriate value of this selection bias because it varies for each problem instance. In this paper, a biasless selection scheme for the SE algorithm is proposed. This scheme eliminates the human interaction needed in the selection of the bias value for each problem instance. Due to the imprecise nature of the design information at the placement stage, fuzzy logic is used in all stages of the SE algorithm. The proposed scheme was compared with an adaptive bias scheme and was always able to achieve better solutions.

We engineer a well-known optimization technique namely tabu search (TS) (Sait and Youssef, 1999) for the performance and low power driven VLSI standard cell placement problem (Sait and Youssef, 1995; Minhas, 2001). The above problem is of multiobjective nature since three possibly conflicting objectives are considered to be optimized subject to the constraint of layout width. These objectives are power dissipation, timing performance, and interconnect wire length. It is well known that optimizing cell placement for even a single objective namely total wire length is a hard problem to solve. Due to the imprecise nature of objective values, fuzzy logic is incorporated in the design of the aggregating function. The above technique is applied to the placement of ISCAS-89 benchmark circuits and the results are compared with the Adaptive-bias Simulated Evolution (SimE) approach reported in (Youssef et al., 2001). The comparison shows a significant improvement over the SimE approach.

When fuzzy logic is used with multi-objective optimization, min/max operators may not be desirable. This is primarily due to the lack of compensation/submission of min/max. To overcome this, ordered weighted averaging (OWA) operators were proposed by R.R. Yager (1988). OWA requires the selection of a control parameter /spl beta/, which is different for different problem instances. In this paper, we propose new fuzzy aggregating functions that simulate the fuzzy AND/OR logic and that have the advantages of OWA without the need of any control parameter. A comparison with OWA for VLSI cell placement using simulated evolution produced encouraging results.

In this paper we employ fuzzified simulated evolution and stochastic evolution algorithms for VLSI. standard cell placement targeting low power dissipation and high performance. Due to the imprecise nature of design information at the placement stage, the various objectives and constraints are expressed in fuzzy domain. The search is made to evolve towards a vector of fuzzy goals. The proposed algorithms are compared with genetic algorithm.

This paper describes and analyzes the application of a simulated evolution (SE) approach to the problem of matching and scheduling of coarse-grained tasks in a heterogeneous suite of machines. The various steps of the SE algorithm are first discussed. Goodness function required by SE is designed and explained. Then experimental results applied on various types of workloads are analyzed. Workloads are characterized according to the connectivity, heterogeneity, and communication-to-cost ratio of the task graphs. The performance of SE is also compared with a genetic algorithm (GA) approach for the same problem with respect to the quality of solutions generated, and timing requirements of the algorithms. 1.

The topology design of campus networks is a hard constrained combinatorial optimization problem. It consists of deciding the number, type, and location of the active network elements (nodes) and links. This choice is dictated by physical and technological constraints and must optimize several objectives. Example of objectives are monetary cost, network delay, and hop count between communicating pairs. Furthermore, due to the nondeterministic nature of network traffic and other design parameters, the objective criteria are imprecise. Fuzzy logic provides a suitable mathematical framework in such a situation. We present an approach based on the simulated evolution algorithm for the design of campus network topology. The two main phases of the algorithm, namely, evaluation and allocation, have been fuzzified. To diversify the search, we have also incorporated tabu search-based characteristics in the allocation phase of the SE algorithm. This approach is then compared with the simulated annealing algorithm, which is another well-known heuristic. Results show that on all test cases the simulated evolution algorithm exhibits more intelligent search of the solution subspace and was able to find better solutions than simulated annealing.

VLSI standard-cell placement is an NP-hard problem to which various heuristics have been applied. In this work, tabu search placement algorithm is parallelized on a network of workstations using PVM. The objective of the algorithm is to achieve the best possible solution in terms of interconnection length, overall area of the circuit, and critical path delay (circuit speed). Two parallelization strategies are integrated: functional decomposition strategy and multi-search threads strategy. In addition, domain decomposition strategy is implemented probabilistically. The performance of each strategy is observed and analyzed.

A fuzzy simulated evolution algorithm is presented for multi-objective minimization of VLSI cell placement problem. We propose a fuzzy goal-based search strategy combined with a fuzzy allocation scheme. The allocation scheme tries to minimize multiple objectives and adds controlled randomness as opposed to original deterministic allocation schemes. Experiments with benchmark tests demonstrate a noticeable improvement in solution quality.

This paper presents a hardware-efficient memory allocation (EMA) technique designed to eliminate both internal and external fragmentation that appear in the buddy system. EMA can allocate a free memory block of any size in any part of memory. Hardware implementation of EMA is introduced, but only part of its circuits is shown in the paper due to the space limitation. Simulation results show that EMA utilizes memory space more efficiently than the previously known techniques.

In this paper we address the problem of optimizing mixed CMOS/BiCMOS circuits. The problem is formulated as a constrained combinatorial optimization problem and solved using an tabu search algorithm. Only gates on the critical sensitizable paths are considered for optimization. Such a strategy leads to sizable circuit speed improvement with minimum increase in the overall circuit capacitance. Compared to earlier approaches, the presented technique produces circuits with remarkable increase in speed (greater than 20%) for very small increase in overall circuit capacitance (less than 3%).

Partitioning is a very important task in hardware/software co-design. Generally the size of the edge cut-set is used to evaluate the communication cost. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions, and their delays are not considered. In this paper we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the CDFG, and solved as a clique partitioning problem, and (2) the system delay that is estimated using List Scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm called Problem-Space Genetic Algorithm to search for the optimum. Results are compared with those produced by simulated annealing.

No abstract available.

Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of /spl alpha/-criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20%.

Network folding is a technique for realizing permutations on N elements using interconnection networks with M input (and output) terminals, where M>

Petri nets are popular in the communication protocol community for modelling and analysis purposes. This paper gives a procedure for extraction and implementation of controllers of protocols from their Petri net model. It adds another dimension to the use of Petri nets and is suited for network, transport and data link protocols.>