Demo Data from VLDB 2026 / reviewers in the wild / expert
Eiji Kuno
dblp:43/271
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1986
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 87% Interconnection networks and networks-on-chip · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › multiprocessor system
parallel inference machine |
0.0 | 1 | 1986 | The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D · ISCA 1986 |
Parallel and multicore computing › parallel computing › parallel programming languages
parallel logic programming |
0.0 | 1 | 1986 | The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D · ISCA 1986 |
Interconnection networks and networks-on-chip › network topology
hierarchical interconnection network |
0.0 | 1 | 1986 | The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D · ISCA 1986 |
Methods — techniques the papers use, named apart from their topics
performance evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1986 | The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-DabstractA parallel inference machine based on the dataflow model and the mechanisms to support two types of logic programming languages are presented. The machine is constructed from multiple processing elements and structure memories interconnected through a low-latency hierarchical network. The preliminary evaluation results of the experimental machine are also presented. The evaluation results show that the machine can exploit parallelism in programs. Noriyoshi Ito, Masatoshi Sato, Eiji Kuno, Kazuaki Rokusawa |
ISCA | 3 |