MPEG-4 High-Efficiency Advanced Audio Coding (HE-AAC) has adopted spectral band replication (SBR) to efficiently compress the high-frequency part of the audio. In SBR, linear prediction is applied to low-frequency subbands to suppress tonal components and smooth the associated spectra for replicating to high-frequency bands. Such a tone-suppressing process is referred to as whitening filtering. In SBR, to avoid the alias artifact incurred by spectral adjustment, a complex filterbank instead of real filterbank is adopted. For QMF subbands, this paper demonstrates that the linear prediction defined in the SBR standard results in a predictive bias. A new whitening filter, called the decimation-whitening filter, is proposed to eliminate the predictive bias and provide advantages in terms of noise-to-signal ratio measure, frequency resolution, energy leakage, and computational complexity for SBR.

This letter proposes a fast radix-$q$ algorithm to compute type-IV discrete cosine transform (DCT) of the length $q ^{\lambda}$, where $q$ is an odd positive integer. The proposed fast radix- $q$ algorithm has merits in computational complexity, parallelism, and numerical stability over existing algorithms. Furthermore, the fast radix-$q$ algorithm is used to develop the fast mixed-radix type-II/type-IV DCT algorithm for composite lengths.

Perceptual audio coding achieves a high compression ratio by exploiting the perceptual irrelevance and data redundancies. By using advanced and sophisticated signal processing methods, perceptual coding has generated artifacts that are quite different from the traditional distortions. A new audio technology becomes mature through the successful modeling, measuring, and control on the artifacts incurred from the technology. With the advance of new coding modules in advanced audio coding (AAC), spectral band replication (SBR), and parametric coding, the incurred artifacts are far more difficult to model, measure, and control than those caused by previous encoding systems like pulse code modulation. This paper models the audible artifacts through the time-frequency diagrams, considers the artifacts-susceptible music types, and analyzes the critical encoding technologies incurring these artifacts.

A subsampling structure, an N-Queen lattice, for spatially decimating a block of pixels is presented. Despite its use for many applications, we demonstrate that the N-Queen lattice can be used to speed up motion estimation with nominal loss of coding efficiency. With a simple construction, the N-Queen lattice characterizes the spatial features in the vertical, horizontal, and diagonal directions for both texture and edge areas. Especially in the 4-Queen case, every skipped pixel has the minimal and equal distance of unity to the selected pixel. It can be hierarchically organized for variable nonsquare block-size motion estimation. Despite the randomized lattice, we design compact data storage architecture for efficient memory access and simple hardware implementation. Our simulations show that the N-Queen lattice is superior to several existing sampling techniques with improvement in speed by about N times and small loss in peak SNR (PSNR). The loss in PSNR is negligible for slow-motion video sequences and is less than 0.45 dB at worst for high-motion estimation sequences.

We present a novel technique, N-queen lattice, to spatially subsample a block of pixels. Although this lattice is pertinent to many applications, we present an application to speed up motion estimation with minimal loss of coding efficiency. The N-queen lattice is constructed to characterize spatial features in all directions. It can be hierarchically organized for motion estimation with variable nonsquare block size. Despite the randomized lattice structure, we demonstrate that it is possible to achieve compact data storage architecture for efficient memory access and simple hardware implementation. Our simulations show that the N-queen lattice is superior to several existing sampling techniques with improvement in speed by about N times and small loss in peak SNR.

This paper considers the design of a vocabulary-independent keyword spotter for Mandarin speech according to the framework by Huang et al. (1994). This paper considers three varieties of filler model structures for the framework based on subsyllabic grammar of Mandarin speech. On the basis of the three structures, we infer the problems of this framework through three arguments and presents two methods to modify the spotting vehicle.

This paper presents a novel VLSI array design for the 1-D discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, we develop an algorithm which can formulate the 1-D any-length DHT as cyclic convolutions. This algorithm owns higher flexibility in the transform length as compared with the existing approach of Guo, Liu, and Jen (see Proc. IEEE International Conference on Acoustics; Speech, and Signal Processing, p.v.621-v.624, 1992 and IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.30, p.723-733, Oct. 1992). Moreover, we use the memory-based approach to realize the cyclic convolutions by systolic arrays and implement the multiplications by small ROMs and adders. The presented array not only outperforms the distributed arithmetic (DA) architectures in the hardware area, but also owns low input/output (I/O) cost, power dissipation, high computing speeds and flexibility in transform length.>

Maneuvering tracking involves tracking a target that is suddenly accelerated by the pilot. Two approaches have been proposed for maneuvering target tracking: the residual-based approach and the multiple-model approach. The latter approach provides better tracking performance but has higher computational complexity compared with the former one. The authors present a new maneuvering tracking algorithm which combines the benefits of both approaches so that the tracking accuracy is comparable with that of the multiple-model approach and the complexity with that of the residual-based approach.>

In this paper, a general memory-based approach to design VLSI arrays for the multi-dimensional (M-D) discrete Hartley transform (DHT) with any length is proposed. There are four parts of this approach: (1) a new M-D DHT formulation, (2) cyclic convolution representation, (3) systolic array realization, and (4) memory-based implementation. Deriving a new M-D DHT formulation avoids the undesirable overhead required in formal designs. Taking cyclic convolution provides high computing parallelism and low computation complexity. Using systolic array realisation results in high computing speeds and low I/O cost. Adopting the memory-based implementation yields low hardware cost and low power dissipation. In summary the proposed approach will lead to efficient and high-performance VLSI array designs for the M-D DHT.>

The component labeling process basically consists of label-assigning and label-merging steps. Label-assigning step is to give a rough labeling number for each dotted pixel in a binary image and find the equivalent relations for all the labeling numbers. On the basis of these equivalent relations, the label-merging step is to merge these labeling numbers to give a unique number for a connected component. These two steps need immense logical computations and memory accesses, and hence restrict the feasibility of real-time applications. In this paper, we solve this problem through the design of a novel algorithm and VLSI architecture based on an 8-adjacent rule.>

A new design and implementation approach for the discrete Fourier transform (DFT) and discrete cosine transform (DCT) is discussed. The approach, called memory-based approach, is based on a design concept of combining and exploiting both the advantages induced from the systolic array architectures and the efficient implementation techniques of substituting multipliers by read-only-memory (ROM) together. Based on this approach, the proposed arrays feature high computing speeds, low complexity and hardware cost of the processing elements (PEs), and low I/O cost. Moreover, high regularity both among and inside the PEs can be found in the proposed arrays. These merits make the proposed designs much more feasible for VLSI implementation.>

A package, named VLSI array architectures synthesizer (VAAS), to synthesize VLSI array architectures for DSP applications is presented. VAAS has been imbedded with the systematical synthesis method for systolic arrays, two-level pipelined systolic arrays, and multiple-array architectures. It provides a design environment with an algorithm description language, 3D graphical representations, performance evaluation, array simulation, a library of systolic algorithms, etc. Based on the environment, feasible VLSI array architectures for a DSP application can be exploited quickly. Two design examples are used to demonstrate the package.>

Autoregressive (AR) spectral estimation is widely used in various fields. However, a trade-off between performance and computational complexity is sometimes faced. Two recursive computing algorithms individually applied to the wide-sense stationary and highly nonstationary environments are presented. These algorithms have good numerical properties, high computing parallelism, and data locality. VLSI arrays are designed to realize the algorithms. The algorithms and arrays provide the potential of attaining high processing speed and good performance in real-time applications.>

A computationally efficient adaptive algorithm for the IBDA (innovations-based detection algorithm) is devised and realized with a systolic array so that is possesses both fast adaptation and good steady-state performance. The algorithm has superior numerical properties and computational complexity. It possesses high computing parallelism and good data locality, which are preferable in VLSI arrays. One systolic array example designed for the algorithm has an iteration time of (2N+1) and ((n/sup 2/+3n)/2) processing elements, where n is the number of states.>

The authors consider two implementation techniques for building a high-performance image-resampler VLSI chip. First, a two-level pipelined systolic array is designed for image resampling to give high parallelism in computation and high feasibility for VLSI implementation. Second, a modified two-pass resampling scheme is used to decrease the amount of required storage and increase the concurrency between two resampling passes. With the two techniques, the system can provide a throughput of one pixel in a clock period smaller than that for an adder.>