Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. The paper introduces an alternative view of the relationship between scalable technologies and SMPs. Instead of replacing large SMPs with scalable technology, we propose new scalable techniques that allow large SMPs to be tied together efficiently, while maintaining the compatibility with, and performance characteristics of, an SMP. The trade-offs of such an architecture differ from those of traditional, scalable, Non-Uniform Memory Architecture (cc-NUMA) approaches. WildFire is a distributed shared memory (DSM) prototype implementation based on large SMPs. It relies on two techniques for creating application-transparent locality: Coherent Memory Replication (CMR), which is a variation of Simple COMA/Reactive NUMA, and Hierarchical Affinity Scheduling (HAS). These two optimizations create extra node locality, which blurs the node boundaries to an application such that SMP-like performance can be achieved with no NUMA-specific optimizations. We present a performance study of a large OLTP benchmark running on DSMs built from various sized nodes and with varying amounts of application-transparent locality. WildFire's measured performance is shown to be more than two times that of an unoptimized NUMA implementation built from small nodes and within 13% of the performance of the ideal implementation: a large SMP with the same access time to its entire shared memory as the local memory access time of WildFire.

In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy. It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification. Its main feature can be characterized as "What you simulate is what you synthesize." This principle permits a validation of the synthesis results by simulation or even formal verification. CALLAS has been successfully applied on real designs which were implemented in silicon. These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer. The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level.>

The Siemens high-level synthesis system CALLAS was used to synthesize an ASIC for moving-object detection consisting of 3400 equivalent gates. The digital signal processing (DSP) problem was formulated on algorithmic level in the hardware description language DSDL as a three-page algorithm. Only a few days were needed from specification to the chip layout. Design steps included were high-level behavior simulation, library mapping, and standard cell layout generation using a state-of-the-art physical design system. The authors give a brief overview of the CALLAS system, introduce the DSP example, and discuss the synthesis process and the simulations performed.>