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Makoto Kakegawa

dblp:43/4057 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 77% Processor architecture and microarchitecture · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
logic simulation		 0.011988
Logic Simulation System Using Simulation Processor (SP) · DAC 1988
Processor architecture and microarchitecture
special-purpose processor		 0.011988
Logic Simulation System Using Simulation Processor (SP) · DAC 1988

Methods — techniques the papers use, named apart from their topics

simulation processor · 0.0
YearPublicationVenuePosition
1988 Logic Simulation System Using Simulation Processor (SP)
Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato
 DAC4