In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip oorplanning for area and timing improvements.We develop a timing-driven design ow to exploit the interaction between HDL synthesis and physical design tasks.During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information.The goal is to produce area-ecient designs while satisfying the timing constraints.Experiments on a number of industrial designs have demonstrated that by eectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.

In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area.

Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not utilized effectively nor efficiently. Retiming and layout is combined for the first time in this paper. We present heuristics for two key problems: interconnection delay estimation and post-retiming incremental placement. An efficient retiming algorithm incorporating interconnection delay is also proposed. Experimental results show that on the average we can improve the circuit speed by 5:4% targeted toward a 0:5um CMOS technology. Scaling down the technology to 0:1um, as much as 25:6% improvement have been achieved. 1 Introduction Retiming is a sequential logic optimization technique proposed by Leiserson and Saxe [1]. It relocates reg...

In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to 230K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.

In a hardware emulator consisting of multiple field-programmable gate arrays (FPGAs), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time division multiplexing (TDM). TDM allows one physical wire to be shared by multiple logical wires. For TDM to be effective, each transportation of an inter-FPGA signal must be carefully assigned to a slot of the time division. In this note, we show that the phase assignment problem is exactly same as the resource-constrained operation scheduling problem. We adopt the static-list scheduling heuristic for the task, and present some experimental results on a set of benchmark circuits from the MCNC. The experiments show that the proposed method can increase the number of effective I/O pins as many as ten times.