We describe ways to use fail data from many failing integrate circuits (ICs) to determine which ICs failed because of similar causes, rather than to determine the cause of each individual failing IC. The purpose of finding clusters of similarly failing ICs is to focus on systematic defects, and to de-emphasize random ones. Once large groups of similarly failing ICs have been identified, a selection of the ICs in each group can be diagnosed using standard diagnostic routines.

A new form of logic diagnosis is described that is suitable for diagnosing fails in combinational logic. It can diagnose defects that can affect arbitrarily many elements in the integrated circuit. It operates by first identifying patterns during which only one element is affected by the defect, and then diagnosing the fails observed during the application of such patterns, one pattern at a time. Single stuck-at faults are used for this purpose, and the aggregate of stuck-at fault locations thus identified is then further analyzed to obtain the most accurate estimate of the identities of those elements that can be affected by the defect. This approach to logic diagnosis is as effective as that of classical stuck-at fault-based diagnosis, when the latter applies, but is far more general. In particular, it can diagnose fails caused by bridges and opens as well as fails caused by regular stuck-at faults.

Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors where all inputs have a fanout of two. We show how graph theory can be used to model compactors and design compactors with robust non-aliasing properties that have minimal area and delay overhead and are independent of the test set, the fault model, and the circuit tested.

A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.

The correlation between the delays of various types of paths on an Integrated Circuit (IC) is studied. The correlation between delays of different critical paths is found to be low. An estimate is made of the correlation between the maximum frequency at which the IC can operate and the delay of some specific path on it. This correlation improves as the number of critical and near critical path increases, but will never be perfect.

Technological advances such as flip-chip packaging, multiple hierarchical wiring planes, and ultra-high frequencies reduce the effectiveness of conventional diagnostic techniques. It has recently been demonstrated that light pulses emitted during circuit switching can be used to characterize the behaviour of integrated circuits. In this paper, a new method of circuit characterization using this technique is described. An example of the diagnosis of a timing failure caused by a resistive path to a single transistor is described.

This paper addresses problems associated with the production and interpretation of traditional fault coverage numbers. The first part addresses the issue of non-uniform distribution of detected faults. It is shown that there is a large difference in final quality between covering the chip all over and leaving parts relatively untested, even if the coverage is the same in both cases. The second part deals with the use of weighted, rather than unweighted fault coverages and investigates the use of readily-available extracted capacitance information to produce a weighted fault coverage which is more useful for producing quality estimates, without having to perform a full defect analysis. Results show significant differences in weighted versus unweighted coverages, and also that these differences can be in either direction.

We generalize directed loop networks to loop-symmetric networks in which there are N nodes and in which each node has in-degree and out-degree k, subject to the condition that 2/sup k/ does not exceed N. We show that by proper selection of links one can obtain generalized loop networks with optimal or close to optimal diameter and connectivity. The optimized diameter is less than k/spl lsqb/N/sup 1/k//spl rsqb/, where /spl lsqb/x/spl rsqb/ indicates the ceiling of x. We also show that these networks are rather compact in that the diameter is not more than twice the average distance. Roughly 1/2(k/spl minus/1)N/sup 1/k/ nodes can be removed such that the network of remaining nodes is still strongly connected, if all remaining nodes have at least one incoming and one outgoing link left. >

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 bytes per gate. The low memory requirements and high performance have been achieved by working with a larger but simpler search space, by simplifying decision making and backtracking and by using only implication techniques that are fast and that require no preprocessing.

The authors describe a novel parallelization technique for fault simulation that is suited for message-passing-based parallel processors. The problem is parallelized by first casting it in data-flow form and then constructing a data-flow emulator for message-passing systems. By letting the number of nodes in the parallel processor grow linearly with C, the size of the design, the fault simulation time on a mesh-connected processor grows only as C/sup r+ delta -0.5/, rather than as C/sup 1+ delta /, as on a uniprocessor; r is Rent's exponent and is less than 1.0 and typically on the order of 0.7, and delta is a small positive constant on the order of 0.5 or less. The algorithm has been implemented and exercised on the IBM VICTOR multiprocessor. The performance has been measured for several logic designs as a function of the number of nodes in the parallel processor.>

SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady-state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.>

The testability by random test patterns of faults in the logic surrounding embedded RAMs is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM.>

We describe SLS, a large capacity, high performance switch level simulator, developed to run on an IBM System/370 architecture, that uses a model which closely reflects the behavior of MOS circuits. This performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.