This paper focuses upon assessing the use of Google's NotebookLM for AI-assisted grading of a project assignment weighing 50 % of the final grades obtained by a class of 30 students in a Hardware/Software Codesign course that belongs to a master program in Computer Science. The work complements an existing strategy for AI-assisted learning, shifting the focus from the students' to the teachers' side. NotebookLM's potential contribution to improve teaching activities is briefly considered, followed by the presentation of an experiment where this tool was used to support the teacher's assessment work, and of the students' perception towards AIassisted grading. The paper closes with a brief reflection upon the impact of these emerging technologies upon the wider higher-education sector.

This paper presents a strategy designed to evaluate AI-supplemented teaching and learning in a course belonging to a master program in Computer Science at the University of South-Eastern Norway. The strategy was closely related to the delivery format adopted in this program, where students take only one course at a time. Each course lasts for 6 weeks, comprising an initial “reading week”, an “intensive lectures” week, a 3-week “project assignment”, and one “assessment week”. The university supported the cost of OpenAI Plus account subscriptions offered to each student while the course was running, and specific activities were proposed to the class exploring the different ways in which AI tutoring could be used during each one of the 4 phases included in the course work plan. The strategy can be adapted to other program delivery formats by redistributing the proposed activities in accordance with the planned sequence of learning activities. It is also independent of which generative AI tool is selected, although OpenAI Plus accounts allow access to specific features that offer relevant pedagogical benefits, e.g., a simple process to create private language models that are easily customizable to each course subject.

This paper presents a tool that improves the learning effectiveness of educational/instructional videos by automatically generating an hyperlinked multimedia structure created by 1) analyzing the audio stream to extract a textual description; 2) carrying out semantic analysis to identify the main subjects addressed; 3) identifying keywords and keyframes, and creating a navigational structure that allows the viewers to consume the content in a non-linear and multimodal manner and jump directly into those parts they are mostly interested to watch. The tool performs transformation and automatic curation of any video, allowing the viewers to explore its content in a non-linear form. It can be applied to any type of videos, but it is of particular value in the educational sector, where videos are frequently viewed in parts, and revisited frequently to recall specific aspects of a lecture/topic.

This paper presents the teaching and learning model adopted in an industry-supported master program in Computer Science (MACS/MACSI) and discusses the importance of learning analytics to cope with the challenges posed by a delivery model where the courses run serially over 6 weeks (instead of running in parallel). This model was well received by the students, but calls for innovative pedagogical methods, where flexibility is particularly important for those students that are working in the partner companies. The long-term goal is to offer the same teaching and learning experience to both students and teachers, regardless of their location (on-campus or online), while offering an educational experience that is relevant both for the students and for their industry employers.

This paper describes an initiative that brings together the University of South-Eastern Norway (USN), its student representative body Student Democracy (SDSN), and the Dresser-Rand AS (D-R) engineering and manufacturing company (now called Siemens Oil and Gas) with the objective of creating modular 1-ECTS eXtended Reality (XR) learning packages (LP) created to build a continuum between the shop floor and the classroom. These LPs will not only be offered as part of standard USN bachelor and master programs, but also as continuing education for D-R employees. XR and other cloud technologies are used to create innovative education and training content, and at the same time to help close the gap between the classroom and the shopfloor, by enabling USN academic staff to interact live with company trainees during on-the-job training, and by enabling industry experts to interact live with students in USN classrooms.

In this paper, we present a description of our developed adapter, which takes acts as a gateway between IEEE 1149.1 and IEEE 1149.7 test infrastructures. The referred adapter reduces the pins of the TAP from 4 to 2 and implements advanced capabilities, such as Parking State of a TAPC and the Reset and Selection Unit (RSU).

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

This paper presents the first truly non-intrusive structural concurrent test approach, aimed to test partial and dynamically reconfigurable SRAM-based FPGAs without disturbing their operation. This is accomplished by using a new methodology to carry out the replication of active configurable logic blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system.

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

A set of board-level testability blocks is proposed in this paper, with the aim of improving the fault coverage achievable on boards restricted to commercially available BST components. It is shown that a high flexibility and low-cost solution to board-level BIST is possible by combining an HDL-based implementation with the wide availability of medium-complexity PLDs.>