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Heebyung Yoon

dblp:43/5062 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 81% Integrated circuit design · 19%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › hardware verification and test
analog circuit testing
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation
hardware verification and test
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › hardware verification and test › test response compaction
signature analysis
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › hardware verification and test
test response compaction
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998
Electronic design automation › hardware verification and test
fault detection
0.011998
Signature analysis for analog and mixed-signal circuit test response compaction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1998

Methods — techniques the papers use, named apart from their topics

signature analysis · 0.0aliasing probability analysis · 0.0
YearPublicationVenuePosition
2011 Fault Management of Robot Software Components Based on OPRoS
abstract
Component-based robot development has been a vibrant research topic in robotics due to its reusability and interoperability benefits. However, robot application developers using robot components must invest non-trivial amount of time and effort applying fault tolerance techniques into their robot applications. Despite the need for a common, framework-level fault management, the majority of existing robot software frameworks has failed to provide systematic fault management features. In this paper, we propose a fault management method to detect, diagnose, isolate and recover faults based on the OPRoS software framework. The proposed method provides a collective, framework-level management for commonly encountered robot software faults, thereby reducing the application developers' efforts while enhancing the robot system reliability. To verify the effectiveness of the proposed approach, we have implemented a prototype reconnaissance robot using OPRoS components and injected different types of faults. The results of the experiments have shown that our approach effectively detects, diagnoses, and recovers component faults using the software framework.
JongYoung Kim, Heebyung Yoon, Sunghoon Kim 0001, Sang Hyuk Son
ISORC2
1998 Fault detection and automated fault diagnosis for embedded integrated electrical passives
abstract
In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passive. For pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. The poles and zeros of every circuit in this ensemble are extracted. From knowledge of the passive circuit specifications, pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements.
Heebyung Yoon, Junwei Hou, Abhijit Chatterjee, Madhavan Swaminathan
ICCD1
1998 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits
abstract
In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in a hierarchical manner. The effects of parameter variations in one level of design hierarchy on those of the next are mapped through linear and piecewise linear sensitivity functions. The models allow computation of the statistical distributions of the circuit parameters and their correlations. This data is used to determine the critical circuit specifications that must be measured and those that may be eliminated from the testing process.
Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi
VTS1
1998 Signature analysis for analog and mixed-signal circuit test response compaction
abstract
While the design of signature analyzers for digital circuits has been well researched in the past, signature analyzers for analog signals are relatively unknown. The primary difficulty in analyzing signatures for analog signals is that the latter are imprecise in nature. Therefore, deterministic signature analysis schemes, such as those based on finite-field arithmetic using linear feedback shift registers, are unsuitable for analog circuits. In this paper, a novel signature analysis scheme for analog and mixed signal circuits is proposed. The signatures possess the interesting property that if the input analog signal is imprecise within certain bounds (an inherent property of analog signals), then the generated signature is also imprecise within certain bounds. A failure is indicated by the generated signature being different from the expected signature by a margin greater than a predetermined threshold; the larger the effects of the failure, the larger the difference between the generated signature and the expected signature. The probabilities of aliasing and false rejection are also derived. Results for an example filter circuit are presented.
Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3