Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, TLB misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs.

The design and implementation of embedded microprocessors is on the verge of change -with MCM, flip-chip and integrated DRAM/ logic technologies moving from feasible to commercially viable.Embedded DRAM memory provides a high memory bandwidth together with low latency.However, when such a system is extended with further memory, the processor is exposed to a nonuniform memory hierarchy -where some fraction of the total memory has significantly lower access latency than the remainder.In this paper, we evaluate various hardware-orientated approaches to the management of embedded memory.In addition to static page placement and conventional cache functionality, we explore novel memory management schemes that exploit temporal locality while still using the embedded DRAM as part of the physical memory space.Using execution driven simulation of real workloads, we show that this technique can deliver as much as a factor of two speedup over a conventional memory hierarchy.More importantly, we show how the embedded memory can be used to provide both data storage and a caching capability equivalent to a more complex processor device.These results imply that designers of embedded and small-scale systems can achieve significant performance wins, through the use of a combined processor/ memory device and the memory system design proposed.

Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-centric designs invest a lot of power and chip area to bridge the widening gap between CPU and main memory speeds. Yet, many large applications do not operate well on these systems and are limited by the memory subsystem performance.This paper argues for an integrated system approach that uses less-powerful CPUs that are tightly integrated with advanced memory technologies to build competitive systems with greatly reduced cost and complexity. Based on a design study using the next generation 0.25µm, 256Mbit dynamic random-access memory (DRAM) process and on the analysis of existing machines, we show that processor memory integration can be used to build competitive, scalable and cost-effective MP systems.We present results from execution driven uni- and multi-processor simulations showing that the benefits of lower latency and higher bandwidth can compensate for the restrictions on the size and complexity of the integrated processor. In this system, small direct mapped instruction caches with long lines are very effective, as are column buffer data caches augmented with a victim cache.

We present design details and some initial performance results of a novel scalable shared memory multiprocessor architecture. This architecture features the automatic data migration and replication capabilities of cache-only memory architecture (COMA) machines, without the accompanying hardware complexity. A software layer manages cache space allocation at a page-granularity-similarly to distributed virtual shared memory (DVSM) systems, leaving simpler hardware to maintain shared memory coherence at a cache line granularity. By reducing the hardware complexity, the machine cost and development time are reduced. We call the resulting hybrid hardware and software multiprocessor architecture Simple COMA. Preliminary results indicate that the performance of Simple COMA is comparable to that of more complex contemporary all hardware designs.>