This paper presents a design-oriented analysis for the time-interleaved SAR ADC that quantifies different sources of imperfections to provide a unified design framework. This includes both single-channel and interleaving imperfections. A prototype time-interleaved ADC is designed and fabricated in a 28 nm CMOS process to validate the effectiveness of the theory. With one-time foreground timing skew and offset compensation, the 3.5 GS/s 11-bit time-interleaved SAR ADC achieves 55.6 dB SNDR at low input frequency and 54.3 dB SNDR at Nyquist frequency while dissipating 66.0 mW at 1 V supply including 14.8 mW clock buffer power.

This article presents a 26–32-GHz 6-bit bidirectional passive vector modulation phase shifter (PVM-PS) in 40-nm CMOS for phased array systems. The passive phase shifter comprises a center-tap transformer-based quadrature generator/combiner, two 6-bit X-type attenuators, and a differential Wilkinson power combiner/divider. The symmetric design enables bidirectional signal propagation and offers flexible system configuration. Passive switches are sized to optimize the tradeoff among gain variation, insertion loss, and linearity. The phase shifter implemented in 40 nm covers a range of 360° with 5.625° resolution and the rms phase error is between 0.4° and 1.3°. It exhibits <1-dB magnitude imbalance and <1.2° phase imbalance between forward and reverse propagation modes. Its OP1dB is above −1 dBm across the operation frequency.

This paper proposes a successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring a gain-boosting dynamic comparator design and a low-delay SAR logic. The proposed comparator incorporates positive feedback in the pre-amplifier, which enables high gain during the integration phase, thereby improving energy efficiency. Meanwhile, to ensure sufficient settling time for the internal capacitive digital-to-analog converter (CDAC), an asynchronous SAR logic with low logic delay in the SAR logic loop is implemented. Accordingly, a prototype ADC is manufactured using 28-nm CMOS technology, which achieves a power consumption of 860 μW at a 75 MHz sampling frequency. Moreover, the measured signal-to-noise and distortion ratio (SNDR) of the prototype at the Nyquist frequency is 60.9 dB, which translates to a Walden figure of merit (FOMW) of 12.7 fJ/conversion-step.

This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog converter (C-DAC) to adjust the initial voltage of the discharging process, the DTC achieves a fine resolution of$\mu \text{W}$at 50-MHz clock rate. It achieves a fine resolution of 563-fs over a 10-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.14/0.96-LSB, respectively.

This paper presents an analog low-power sub-sampling phase locked loop (PLL) that tackles the reference spur caused by VCO load modulation from the sub-sampling operation. A complete analysis on the binary frequency shift keying (BFSK) effect including the impact of the VCO buffer is provided, followed by practical design guide that achieves the optimum spur/jitter trade-off. The proposed sub-sampling phase detector incorporates an active primary-secondary architecture for improved isolation to suppress the load modulation. The adaptive frequency locked loop (FLL) consumes zero power in the locked state and activates itself once unlocking is detected. The sub-sampling PLL is fabricated in a 40nm CMOS process. It achieves -121.5dBc/Hz phase noise at 1MHz offset frequency and an RMS jitter of 185fs integrated from 10k to 10MHz. The power dissipation is 1.14mW at 0.95V supply with a -254.1dB figure-of-merit. The proposed phase detector results in -73dBc reference spur that is among the lowest in state-of-art works.

This paper presents a wideband 6-12GHz two-stage low noise amplifier (LNA) that utilizes capacitor assisting triple-winding transformer in the inter-stage matching network. The electric coupling introduced by the assisting capacitor expands the design space by allowing independent control of each effective coupling strength of the three coupled inductors. The equivalent negative resistor enhanced by this capacitor improves the quality factor of the inter-stage network at high frequencies, which further improves the overall design trade-off among gain, bandwidth and noise figure. Fabricated in a 130nm SOI CMOS process, the LNA achieves a remarkable 0.8-1.5dB NF,$< $-14dB S11,$< $-8dB S22, -11.8dBm IP$_{\mathbf{1dB}}$and 21.8-23.3dB power gain across the 6-12GHz passband with ±0.75dB ripple while drawing 20mA from a 3.3V supply.