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Jihong Ren

dblp:43/6759 · DBLP profile ↗
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5ranked-venue papers
3as first author
1since 2021 · last 2023
0000-0001-7583-6919ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Integrated circuit design · 39% Electronic design automation · 30% Interconnection networks and networks-on-chip · 15%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › signal integrity
crosstalk mitigation
0.122005
A unified optimization framework for equalization filter synthesis · DAC 2005
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses · DAC 2003
Interconnection networks and networks-on-chip › bus-based interconnection
high-speed bus
0.122005
A unified optimization framework for equalization filter synthesis · DAC 2005
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses · DAC 2003
Integrated circuit design › interconnect
high-speed signaling
0.122005
A unified optimization framework for equalization filter synthesis · DAC 2005
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses · DAC 2003
Electronic design automation
circuit simulation
0.112009
Stochastic steady-state and AC analyses of mixed-signal systems · DAC 2009
Performance modeling and evaluation › markov models
markov chain analysis
0.112009
Stochastic steady-state and AC analyses of mixed-signal systems · DAC 2009
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.112009
Stochastic steady-state and AC analyses of mixed-signal systems · DAC 2009
Integrated circuit design
analog and mixed-signal circuits
0.012009
Stochastic steady-state and AC analyses of mixed-signal systems · DAC 2009
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
phase-locked loop
0.012009
Stochastic steady-state and AC analyses of mixed-signal systems · DAC 2009

Methods — techniques the papers use, named apart from their topics

phasor analysis · 0.1markov chain model · 0.1sparse matrix techniques · 0.1linear programming · 0.1l2 optimization · 0.0l-infinity optimization · 0.0
YearPublicationVenuePosition
2023 Motion Compensation Method Using Direct Wave Signal for CTSR Bistatic HFSWR
abstract
Coast-transmit ship-receive (CTSR) bistatic high-frequency surface wave radar (HFSWR) can fully exploit the flexibility of moving platforms and the anti-interference advantages of bistatic radar. However, the platform motion can cause the spread of target echo in the frequency spectrum and reduction of amplitude, which is not conducive to detection. In this letter, a motion compensation method using a direct wave signal is proposed for CTSR bistatic HFSWR. First, the frequency shift characteristics of direct wave signal and target echo are analyzed by simulation. The simulation results show that the platform motion has a similar modulation form on both target echo and direct wave signal, and their difference is mainly caused by different azimuths. In addition, the direct wave signal is only affected by the platform motion, so it can be used to obtain the platform motion effect. Then, the proposed method uses a direct wave signal as the reference information to estimate and eliminate the phase modulation caused by the platform motion. At last, the effectiveness of the method is verified by the experiment based on simulated and measured attitude data.
Yonggang Ji, Yiming Wang 0004, Weifeng Sun 0003, Xi Zhang 0028, Meicheng Jiang, Jihong Ren, Farui Li
IEEE Geosci. Remote. Sens. Lett.7
2009 Stochastic steady-state and AC analyses of mixed-signal systems
abstract
This paper demonstrates that the steady-state and adjoint sensitivity analyses can be extended to stochastic mixed-signal systems based on Markov chain models. The examples of such systems include digital phase-locked loops and delta-sigma data converters, of which steady-state response is statistical in nature, consisting of an ensemble of waveforms with probability distribution. For efficient Markov-chain analysis, the paper describes three methods that can limit the number of states: a state discretization scheme based on Gaussian decomposition, a state exploration algorithm that discovers the recurrent states, and a state truncation algorithm that eliminates the states with negligible stationary probabilities. The stochastic AC analysis is performed by deriving a first-order ordinary differential equation governing the perturbations in the stationary probabilities and solving it via phasor analysis. In the digital PLL and first-order ΔΣ ADC examples, the number of states was reduced by a factor of 35 and the frequency-domain phase and noise transfer functions were simulated with a 57~22,000x speed-up compared to using transient, Monte-Carlo simulations.
Jaeha Kim, Jihong Ren, Mark Horowitz
DAC2
2005 A unified optimization framework for equalization filter synthesis
abstract
We present a novel method for jointly optimizing FIR filters for pre-equalization, decision feedback equalization, and near-end crosstalk cancellation. The unified optimization problem is a linear program, and we describe sparse matrix techniques for its efficient solution. We illustrate our approach with uni- and bi-directional buses using differential signaling in both intra-board and cross-backplane scenarios.
Jihong Ren, Mark R. Greenstreet
DAC1
2004 A Signal Integrity Test Bed for PCB Buses
abstract
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circuit design, teams with many designers, long design cycles, and expensive test equipment. By building a "scale model" that operates at bit rates of 50-100 Mbits/sec, we obtain order of magnitude reductions in cost and design time. We present a simple, inexpensive test bed implemented using a PC and inexpensive graphics cards. To demonstrate the effectiveness of our test bed, we use it to validate novel methods for synthesizing crosstalk equalization filters.
Jihong Ren, Mark R. Greenstreet
ICCD1
2003 Synthesizing optimal filters for crosstalk-cancellation for high-speed buses
abstract
We present practical algorithms for the synthesis of crosstalk cancelling equalizing filters. We examine designs optimized for the traditional l2 metric and introduce an approach based on the l∞ metric. We compare the two approaches for realistic buses with tight wire spacings. We show bandwidth improvements of up to a factor of 2 using crosstalk cancellation when compared with no filtering or independent pre-emphasis for each wire. Using l∞ optimization, we achieve roughly 50% better performance than the l2 methods. We are aware of only one other published description of crosstalk cancellation for high-performance buses [9]. We believe that our work is the first to show the advantages of l∞ optimization and to consider crosstalk cancellation for more than just nearest neighbours for high-speed buses.
Jihong Ren, Mark R. Greenstreet
DAC1