It has been pointed out that, in many cases, results generated by non-Manhattan channel routers will be better than those generated by Manhattan routers. Non-optimal bubble sort based algorithms for non-Manhattan channel routing have been proposed in the literature by also allowing connections in the +45/spl deg/ and /spl minus/45/spl deg/ directions. In this paper, optimal algorithms are proposed for the two-layer and three-layer non-Manhattan channel routing problems based on an identical problem formulation. The time complexities of our algorithms and the existing algorithm (which produces the best results so far) are O(K/sup 2/ * N) and O(K * N/sup 2/), respectively, where N is the number of terminals (i.e., the length) of the channel and N is the number of routing tracks (i.e., the height) in the channel. K is always less than N, and in most cases is much smaller than N. Clearly, a significant improvement in time complexity over the existing algorithm (which produces the best results so far) is achieved, while ensuring optimality.>

Gate matrix is a style which allows random logic layout to be performed in a regular manner. An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous work which uses dynamic net list and the concept of delayed binding performs only a small subset of the reordering possible with the proposed algorithm. The proposed algorithm uses a net-list-independent technique to determine the gate sequence. An optimized net list is created after the gate sequence is known. The algorithm has a time complexity of O(E log E) for a design with E logic equations. The experimental results show a considerable reduction in layout area.>

Many optimization algorithms have been proposed for layout styles which are dual dependent: that is, the optimization for the layout of the n-transistor network of a CMOS complex gate is dependent on, the p-transistor network and vice versa. A two-stage linear-time optimization algorithm for dual independent layout styles is presented. The first stage is based on a tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization goal is identical to the Euler pathed optimization algorithms metal-metal matrix (M/sup 3/) layout style, and examples of generated layouts are shown. Starting from a switching expression, the proposed algorithm always produces an optimal solution in terms of the number of diffusion breaks, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence to traverse this transistor circuit (second stage).>

An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the gate matrix layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works using net-lists and the concept of delayed binding performed only a small subset of the reordering possible with the proposed algorithm. The algorithm has a time complexity of O(E log E) for a design with E equations. The experimental results show a considerable reduction in layout area. >