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Robert G. Clapp

dblp:43/9175 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0002-1336-428XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% High-performance computing · 44% Memory systems · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
0.112011
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration · FPGA 2011
High-performance computing › scientific computing systems
seismic imaging
0.112011
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration · FPGA 2011
Memory systems
memory wall
0.012011
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration · FPGA 2011

Methods — techniques the papers use, named apart from their topics

architectural optimization · 0.1algorithmic optimization · 0.1
YearPublicationVenuePosition
2024 Spatial Deep Deconvolution U-Net for Traffic Analyses With Distributed Acoustic Sensing
abstract
Distributed Acoustic Sensing (DAS) that transforms city-wide fiber-optic cables into a large-scale strain sensing array has shown the potential to revolutionize urban traffic monitoring by providing a fine-grained, scalable, and low-maintenance monitoring solution. However, the real-world application of DAS is hindered by challenges such as noise contamination and interference among closely traveling cars. In response, we introduce a self-supervised U-Net model that can suppress background noise and compress car-induced DAS signals into high-resolution pulses through spatial deconvolution. Our work extends recent research by introducing three key advancements. Firstly, we perform a comprehensive resolution analysis of DAS-recorded traffic signals, laying a theoretical foundation for our approach. Secondly, we incorporate space-domain vehicle wavelets into our U-Net model, enabling consistent high-resolution outputs regardless of vehicle speed variations. Finally, we employ L-2 norm regularization in the loss function, enhancing our model’s sensitivity to weaker signals from vehicles in remote traffic lanes. We evaluate the effectiveness and robustness of our method through field recordings under different traffic conditions and various driving speeds. Our results show that our method can enhance the spatial-temporal resolution and better resolve closely traveling cars. The spatial deconvolution U-Net model also enables the characterization of large-size vehicles to identify axle numbers and estimate the vehicle length. Monitoring large-size vehicles also benefits imaging deep earth by leveraging the surface waves induced by the dynamic vehicle-road interaction.
Siyuan Yuan, Martijn van den Ende, Jingxiao Liu, Hae Young Noh, Robert G. Clapp, Cédric Richard, Biondo Biondi
IEEE Trans. Intell. Transp. Syst.5
2011 Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration
abstract
Memory-related constraints (memory bandwidth, cache size) are nowadays the performance bottleneck of most computational applications. Especially in the scenario of multiple cores, the performance does not scale with the number of cores in many cases. In our work, we present our FPGA-based solution for the 3D Reverse Time Migration (RTM) algorithm. As the most computationally demanding imaging algorithm in current oil and gas exploration, RTM involves various computational challenges, such as a high demand for storage size and bandwidth, and a poor cache behavior. Combining optimizations from both the algorithmic and architectural perspectives, our FPGA-based solution manages to remove the memory constraints and provide a high performance that can scale well with the amount of computational resources available. Compared with an optimized CPU implementation using two quad-core Intel Nehalem CPUs, our solution achieves 4x speedup on two Virtex-5 FPGAs, and 8x speedup on two Virtex-6 FPGAs. Our projection demonstrates that the performance will continue to scale with the future increase of FPGA capacities.
Haohuan Fu, Robert G. Clapp
FPGA2
2010 Surviving the end of scaling of traditional micro processors in HPC
Olav Lindtjorn, Robert G. Clapp, Oliver Pell, Oskar Mencer, Michael J. Flynn
Hot Chips Symposium2