This paper presents a novel methodology for design space exploration and resource optimisation of three-dimensional Networks-on-Chip (3D NoC) architectures using hypergraph modelling and genetic algorithms. The proposed approach combines mathematical rigour with evolutionary search capabilities to efficiently explore the vast design space of 3D NoC configurations, providing a vendor-independent solution for NoC architects. The key contribution is the development of Performance-Cost-Ratio (PCR) functions that enable quantitative evaluation of different topologies and routing algorithms, extended to include power and thermal considerations with dynamic adaptation mechanisms for runtime traffic variations. Validation through four compute-intensive use cases demonstrates significant improvements, with optimised architectures achieving up to 33% reduction in latency, 40% increase in throughput, and 30% reduction in power consumption compared to baseline implementations. Validation against published silicon implementations shows 92-96% correlation accuracy, confirming the framework’s practical applicability for developing efficient and scalable NoC solutions as processor designs advance towards kilo-core scales and beyond.