Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Jiajun Luan

dblp:435/7807 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0009-1881-2350ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Software-defined and programmable networks · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks
programmable data plane
1.012026
Mitigating CPU Frontend for Complex Data Plane Applications · NSDI 2026
Processor architecture and microarchitecture
front-end
1.012026
Mitigating CPU Frontend for Complex Data Plane Applications · NSDI 2026
YearPublicationVenuePosition
2026 Quanta: Scaling Packet-Level Network Simulation by Exploiting Execution Redundancy
abstract
Packet-level network simulation provides high-fidelity modeling but suffers from severe scalability bottlenecks. Existing scaling approaches remain inefficient for modern data-center and AI-training networks. Spatial parallelism requires substantial hardware resources, while temporal-skipping approaches become less effective under bursty traffic. We observe that homogeneous data-center deployments introduce substantial execution redundancy during simulation.
Jiajun Luan, Hao Li 0011, Yihan Dang, Ze Xia, Danfeng Shan, Peng Zhang 0011
APNet1
2026 Mitigating CPU Frontend for Complex Data Plane Applications
Yihan Dang, Hao Li 0011, Ze Xia, Jiajun Luan, Peng Zhang 0011
NSDI4