Fault-tolerant reconfiguration is essential for improving the reliability and efficiency of multiprocessor arrays. However, existing reconfiguration approaches primarily focus on algorithmic optimization, often neglecting architectural imbalance and communication bottlenecks arising from asymmetric redundancy placement. To overcome these limitations, this paper proposes an efficient framework that combines a novel double-sided redundant architecture with two-stage optimization algorithms to enhance interconnect efficiency under permanent processing element (PE) faults. The proposed$R_{l}+M+R_{r}$architecture symmetrically distributes redundant columns on both sides of the array while maintaining the same total number of spare PEs as single-sided redundancy, thereby mitigating unbalanced compensation paths and long communication distances without increasing hardware cost. Based on this structure, a shortest-path fault compensation algorithm is developed to minimize inter-PE communication distances, and a wide Tabu-based optimization algorithm is introduced as a second-stage refinement for global exploration and multi-directional reconfiguration. Experimental evaluations demonstrate that the proposed framework achieves superior communication performance and scalability compared with state-of-the-art methods under both single-sided and double-sided redundant architectures. It achieves lower latency, higher throughput, and reduced energy consumption while maintaining identical redundant resources and a smaller interconnect area footprint, confirming the efficiency and practicality of the proposed fault-tolerant topology reconfiguration strategy.