IBM Telum is the next generation processor chip for IBM Z and LinuxONE systems. The Telum design is focused on enterprise class workloads and it achieves over 40% per socket performance growth compared to IBM z15. The IBM Telum is the first server-class chip with a dedicated on-chip AI accelerator that enables clients to gain real time insights from their data as it is getting processed.

A promising candidate for sensitive imaging of breast cancer is 3D Ultrasound Computer Tomography (3D USCT). So far its clinical applicability for diagnosis has been limited by the duration of the demanding image reconstruction. In this paper we investigate how signal processing and image reconstruction can be accelerated for diagnosis by using heterogeneous hardware. Additionally, the time and costs for real-time system for a future diagnosis and therapy device is estimated. Reusing the device's built-in FPGA-based data acquisition system (DAQ) through reconfiguration results in a speed-up by a factor of 7 for signal processing and by a factor of 2 for image reconstruction. Applying cutting-edge single FPGAs and GPUs, speed-ups by a factor of 10 (FPGA) and 6 (GPU) for signal processing and 15 (FPGA) and 37 (GPU) for image reconstruction were achieved compared to a recent quad-core Intel Core-i7 CPU. Using quad-core CPUs and a cluster of eight GPUs allowed us for the first time to calculate volumes in less than 30 min with an overall speed-up by a factor of 47, enabling a first clinical study. Based on these results we extrapolated that real-time reconstruction for a therapeutic 3D USCT will be possible in the year 2020 if the trend in density follows the ITRS roadmap.

Field programmable Gate Arrays (FPGAs) promise a low power flexible alternative for implementing parallel applications. Compared to CPUs and GPUs, they suffer from slow development cycles due to the high complexity of application development and hardware incompatibilities. Towards this direction, we propose a platform-independent methodology and the supporting framework targeting efficient run-time application mapping onto FPGAs. Experimental results show that the introduced solution performs application placement and routing of multiple applications without any performance penalty as compared to state of art tools. Scalability of the framework was verified by mapping up to 73 applications per minute when it is executed on an 8 core system.