The Hough transform is a well known technique for detecting straight lines within images, especially in the presence of noise, or where there is incomplete data (gaps or occlusions). When subjected to lens distortion, straight lines become curved, and indeed this can be used to identify and correct lens distortion. However, curved lines distort and blur the peaks within the Hough transform, making the lines more difficult to detect. However, by analysing the distortion within the Hough transform, it is possible to directly estimate the lens distortion parameters enabling the distortion to be corrected in real time. The proposed technique uses a Terasic DE1-SoC FPGA board (Cyclone V FPGA) to fit a parabola to the distorted peak using Hough's original transform, and from the parabola coefficients directly estimates the lens distortion parameter. This enables the following frame to be corrected in parallel with curve detection.

In computer vision, blob detection is used to obtain regions of interest that could signal the presence of objects or parts with application to object recognition and object tracking. One of the more common blob detectors is based on the Laplacian of Gaussian (LoG). However, most blob detectors developed in the past assume circular blobs, and these detectors do not perform as well with elliptical blobs, a more prevalent scenario in real images. A generalised LoG (GLoG) detector was proposed recently to deal specifically with elliptical blobs. To formulate the GLoG in a multi‐scale framework, its response must be made scale invariant. Toward that end, necessary and sufficient conditions are presented here, with the normalisation factors derived for a scale‐invariant GLoG detector. The factors are validated with a synthetic example and are further tested with two real‐world images.

While there have been several implementations of the Hough transform on FPGA, one common problem is how to efficiently reconstruct the lines onto an output video stream. This paper uses a simplified Canny filter for preprocessing, then performs a parallel Hough transform, with a small dedicated processor associated with each angle bin. Logic is optimised using incremental addressing associated with the streamed input. Peaks are detected during vertical blanking, while clearing the Hough transform accumulators. Detected peaks are marked in the parameter memory, enabling the lines to be directly reconstructed by back projection while transforming the next frame. This novel back-projection technique enables any number of lines to be reconstructed directly from their parameters with no additional logic, and only one additional memory bit per Hough transform bin.

A real-time image filtering technique is proposed which could result in faster implementation for fingerprint image enhancement. One major hurdle associated with fingerprint filtering techniques is the expensive nature of their hardware implementations. To circumvent this, a modified anisotropic Gaussian filter is efficiently adopted in hardware by decomposing the filter into two orthogonal Gaussians and an oriented line Gaussian. An architecture is developed for dynamically controlling the orientation of the line Gaussian filter. To further improve the performance of the filter, the input image is homogenized by a local image normalization. In the proposed structure, for a middle-range reconfigurable FPGA, both parallel compute-intensive and real-time demands were achieved. We manage to efficiently speed up the image-processing time and improve the resource utilization of the FPGA. Test results show an improved speed for its hardware architecture while maintaining reasonable enhancement benchmarks.

The horizon effect of truncating the search tree within Trax can be overcome by detecting complex threats within a single evaluation. This requires recognising the tile patterns associated with complex threats. The application of equivalence principles enables two-dimensional patterns to be reduced to a one-dimensional end representation, with pattern detection becoming one of recognising one-dimensional template patterns. A hierarchical state machine based matching process is proposed which can match multiple patterns in parallel, processing the position at one end per clock cycle. This enables the evaluation of over 1 million moves per second, facilitating high speed game tree exploration.

A resource-efficient hardware architecture for connected component analysis (CCA) of streamed video data is presented, which reduces the required hardware resources, especially for larger image widths. On-chip memory requirements increase with image width and dominate the resources of state-of-the-art CCA single-pass hardware architectures. A reduction in on-chip memory resources is essential to meet the ever increasing image sizes of high-definition (HD) and ultra-HD standards. The proposed architecture is resource efficient due to several innovations. An improved label recycling scheme detects the last pixel of an image object in the video stream only a few clock cycles after its occurrence, allowing the reuse of a label in the following image row. The coordinated application of these techniques leads to significant memory savings of more than two orders in magnitude compared with classical two-pass connected component labeling architectures. Compared with the most memory-efficient state-of-the-art single-pass CCA hardware architecture, 42% or more of on-chip memory resources are saved depending on the features extracted. Based on these savings, it is possible to realize an architecture processing video streams of larger images sizes, or to use a smaller and more energy-efficient field-programmable gate array device, or to increase the functionality of already existing image processing pipelines in reconfigurable computing and embedded systems.

Smart cameras are cameras which not only perform the sensing, but also integrate much of the image analysis and control. This paper describes the replacement of a conventional vision system within a Trax playing robot with an FPGA based smart camera. Integrated within the camera are the following functions: camera calibration, tile detection and localization, human player detection, robot control, and game play. The result is that the smart camera not only captures the images, but also analyses the image data and performs all of the functionality required to run the robot completely autonomously.

Demosaicing is the process of interpolating the output from a single chip colour filter array sensor to form a full colour image. In hardware, the simplest algorithms: zero order hold and bilinear interpolation, are commonly used because of their simplicity and low resource requirements. State of the art algorithms are difficult to implement in hardware because of their complex access patterns. This paper explores the streamed implementation of a higher order interpolation filter, with a weighted median classifier. Although this comes at a cost of a factor of 10 increase in hardware resources, and a reduction in maximum pixel clock frequency by 30%, this state of the art algorithm gives considerably improved images of 11.2 dB in peak signal to noise ratio with a considerable reduction in interpolation artifacts. For real-time applications where image quality is critical, an implementation of such an advanced demosaicing algorithm on FPGA is essential.

In this paper, an adaptive architecture for dynamic management and allocation of on-chip FPGA Block Random Access Memory (BRAM) resources is presented. This facilitates the dynamic sharing of valuable and scarce on-chip memory among several processing elements (PEs), according to their dynamic run-time memory requirements. Different real-time applications are becoming increasingly dynamic which leads to unexpected and variable memory footprints, and static allocation of the worst-case memory requirements would result in costly overheads and inefficient memory utilization. The proposed scalable BRAM memory management architecture adaptively manages these dynamic memory requirements and balances the buffer memory over several PEs to reduce the total memory required, compared to the worst-case memory footprint for all PEs. The run-time adaptive system allocates BRAM to each PE sufficiently fast enough as required and utilized. In a case study, a significant improvement in BRAM utilization with limited overhead has been achieved due to the adaptive memory management architecture. The proposed system supports different BRAM types and configurations, and automated dynamic allocation and deallocation of BRAM resources, and is therefore well suited for the dynamic memory footprints of FPGA-based reconfigurable architectures.

A memory efficient architecture for single-pass connected components analysis suited for high throughput embedded image processing systems is proposed which achieves a high throughput by partitioning the image into several vertical slices processed in parallel. The low latency of the architecture allows reuse of labels associated with the image objects. This reduces the amount of memory by a factor of more than 5 compared to previous work. This is significant, since memory is a critical resource in embedded image processing on FPGAs.

The problem of mapping from a high dynamic range image, or a series of images spanning a wide dynamic range, to a standard 8-bit image is considered. Several techniques for dynamic range compression are reviewed. FPGA implementations are developed and demonstrated, with a focus on directly processing the video stream from the camera.

Morphological filters are often implemented using a series decomposition. This paper presents a parallel decomposition that is able to exploit separability. By maximising the reuse of hardware between the parallel filters, a novel computationally efficient filter structure may be derived. Results show that such filters may be implemented on a Virtex-5 FPGA with pixel clock rates approaching 1 GHz.

Foveal vision reduces the data volume by utilising a spatially variant resolution. A high resolution is maintained in the fovea where it can be used by computer vision algorithms, while the resolution is reduced in the periphery where it is less important. This work focuses on the hardware architecture of a system that maps a conventional high resolution uniformly sampled sensor to a variable resolution output. The key feature of the proposed architecture is that it employs a separable forward mapping which requires a small amount of FPGA resources. This enables an efficient implementation of a continuously variable spatial resolution, requiring only 1000 LUTs on a Virtex-5, and runs at 104 MHz, enabling the mapping of a 512 × 512 window at over 300 frames per second.

Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. The basic requirements of connected components analysis are investigated, and this led to a novel single-pass approach that avoids the need to buffer an intermediate image. This is further analysed to give an algorithm that is both memory efficient and has the minimum latency. The final algorithm reduces the memory by over 300 times, and reduces the latency by more than a factor of 2.

Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. Recently, a single-pass algorithm was proposed that avoided the need to buffer an intermediate image. In this paper, a new single pass algorithm is described that is a considerable improvement over the existing algorithms. The new algorithm reassigns and reuses labels each row to minimise the size of both the equivalence and region data tables. The optimised single-pass algorithm reduces the worst case memory requirement by over 100 times that of the original algorithm (for measuring region area), and reduces the latency to only 1 row.

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation.

Filtering is often used in image processing to smooth noise, and to enhance or detect features within an image. Images which have regular patterns in the spatial domain have peaks in the frequency domain corresponding to the spatial frequencies of the regular patterns. When processing such images, it is often desirable to keep such peaks, enhancing the pattern and removing noise or irregularities. This is effectively a bandpass filtering operation. The problem with such filtering is that it requires a priori knowledge of the contents of the image so that the filter can be 'tuned' to select the appropriate frequencies. Self-filtering overcomes this by multiplying the frequency domain image with its own magnitude. This gives a bandpass filter that is automatically tuned to the frequency content of the image. Applications included detecting and enhancing regular patterns; interpolating or extrapolating regular patterns; and smoothing or reducing noise.

On a bi-level colour device, only eight distinct colours (including black and white) are able to be represented. One common method of mapping image data to such a device is to use error diffusion techniques. These techniques diffuse the error from representing a particular pixel to adjacent unprocessed pixels, with the effect that locally the average pixel value closely approximates that of the original image. However when applied to colour images, the pattern of dots within the three colour planes loose synchronisation, resulting in coloured patterns within regions of low saturation. This paper demonstrates that this problem may be overcome by modulating the threshold level by the image intensity. The results presented show that a threshold deviation on 15% is sufficient to give the desired linear relationship between desynchronisation and saturation, and that the resynchronisation occurs within one or two pixels of an edge between a saturated and unsaturated region.

To study the morphology of coastal sandbars and their change with time, it is necessary to obtain a sequence of maps over the period of interest. Traditional techniques such as vertical aerial photography or echo-sounding over a grid are expensive and subject to environmental constraints, especially in higher energy situations. Image processing is used to rectify elevated terrestrial images where morphological features are inferred from breaking wave patterns. As the coordinates of interest are longshore and offshore distances, the image is then warped to make the coastline straight. The sandbar crest positions within this image are detected. An error analysis shows that useful quantitative data may be obtained. The temporal evolution of the bars can be identified from time stack images.