A new cache coherence solution is proposed for an over 500 MHz on-chip multiprocessor using advanced VLSI technology. In order to reduce shared-bus transaction time, the central coherence unit (CCU) is introduced. The CCU controls all shared-bus transactions, monitoring all cache rays every clock cycle, and executes a bus transaction in four clock cycles while a conventional bus mechanism requires eight clock cycles. A new cache coherence protocol (CRAC) is also introduced in order to reduce external memory access. The CRAC protocol makes it possible to load a desired data from any cache having a copy, and to transfer write-back responsibility to another cache having a copy. An implementation of CCU and CRAC is presented and evaluated using a cycle-based multiprocessor simulator. Simulation results show that introduction of CCU and CRAC is effective to reduce shared-bus traffic and total execution time. Furthermore, proposed multiprocessor model with CCU and CRAC is proved to be more scalable than a conventional multiprocessor model.

A shared radix 2 division and square root implementation using a self-timed circuit is presented. The same execution time for division and square root is achieved by using an on-the-fly digit decoding and a root multiple generation technique. Most of the hardware is shared, and only several multiplexers are required to exchange a divisor multiple and a root multiple. Moreover, quotient selection logic is accelerated by a new algorithm using a 3-b carry propagation adder. The implementation of the shared division and square root unit is realized by assuming 0.3 /spl mu/m CMOS technology. The wiring capacitance and other parasitic parameters are taken into account. The execution time of floating point 55-b full mantissa division and square root is expected to be less than 30 ns in the worst case of an input vector determined by an intensive circuit simulation.>