Demo Data from VLDB 2026 / reviewers in the wild / expert
Wolfgang Kleinöder
dblp:44/3303
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Computer networks · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 38% Parallel and multicore computing · 28% Memory systems · 19% | |
| Computer networks
1 paper |
Network management and operations · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Network management and operations
network management system |
0.0 | 1 | 1985 | CNMGRAF--graphic presentation services for network management · SIGCOMM 1985 |
Performance modeling and evaluation
workload characterization |
0.0 | 1 | 1983 | Experiences with Performance Measurement and Modeling of a Processor Array · IEEE Trans. Computers 1983 |
Parallel and multicore computing
array processor |
0.0 | 2 | 1983 | Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA · ISCA 1980 Experiences with Performance Measurement and Modeling of a Processor Array · IEEE Trans. Computers 1983 |
Memory systems
memory interference |
0.0 | 1 | 1980 | Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA · ISCA 1980 |
Performance modeling and evaluation
benchmarking |
0.0 | 1 | 1983 | Experiences with Performance Measurement and Modeling of a Processor Array · IEEE Trans. Computers 1983 |
Interconnection networks and networks-on-chip
network topology |
0.0 | 1 | 1983 | Experiences with Performance Measurement and Modeling of a Processor Array · IEEE Trans. Computers 1983 |
Interconnection networks and networks-on-chip › multiprocessor interconnection
processor-memory interconnection |
0.0 | 1 | 1980 | Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA · ISCA 1980 |
Methods — techniques the papers use, named apart from their topics
performance modeling · 0.0performance measurement · 0.0hardware measurement · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | CNMGRAF--graphic presentation services for network managementabstractTwo key problems in the design of systems and network management applications are: how to efficiently manage large quantities of related data, and how to allow the application user to view this data at a user-defined level of detail. This paper describes an architecture for network management facilities that may help solve these problems. It also describes CNMgraf (Communications Network Management Graphics Facility), which was developed to test the presentation service model defined by this architecture. Richard S. Gilbert, Wolfgang Kleinöder |
SIGCOMM | 2 |
| 1983 | Experiences with Performance Measurement and Modeling of a Processor ArrayabstractThe evolution of technology provides the opportunity of forming large processor ensembles working closely together. When decomposing application programs and assigning subtasks to different processors we expect not only high throughput, but also the fastest possible execution of each individual demand. The level of performance in these areas is strongly influenced by the hardware interconnection structure and by the communication software. Hansjörg Fromm, Uwe Hercksen, Ulrich Herzog, Karl-Heinz John, Rainer Klar, Wolfgang Kleinöder |
IEEE Trans. Computers | 6 |
| 1980 | Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPAabstractThe contemporary general purpose computer of the Princeton type is limited in its performance by the speed of the available logic families. Many projects around the world try to achieve higher performance by using many processors connected via common memories. The hardware costs for the interconnection of many processors and memories has to be limited and a severe degradation resulting from memory access conflicts must be avoided. The EGPA-project uses the concept of restricted neighbourhoods to solve these problems. The processors and memories are arranged in a freely extensible cellular structure. The number of connections to processors and to memories are limited for all sizes of the array. In this paper we present measured results from the pilot system, which show whether memory conflicts will influence the speed of the individual processors. The results will be valid for larger arrays, too. Uwe Hercksen, Rainer Klar, Wolfgang Kleinöder |
ISCA | 3 |