This paper describes a camera-less eye-tracker using an instrumented contact lens fitted with photodetectors and illuminated by eyewear. The gaze direction is computed on the lens using the photo-currents by means of a mixed signal 0.35$-\mu$m CMOS ASIC. NFC is used to power the ASIC and to transmit the gaze direction to the eyewear. Experimental measurements are performed using a prototype scleral contact lens mounted on a mock-up eye. The measurements show that an accuracy of 0.2$^{\mathrm{\circ}}$ is achievable, i.e. 2.5 times better than current mobile video-based eye-trackers, for a power consumption of 170 $\mu$W. Several tests were carried out on several ASICs, demonstrating system reliability despite process variations, operating time, and supply voltage variations.

Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low energy budget. This paper proposes a flexible and iterative neural architecture able to implement multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in a ST 65-nm CMOS ASIC and validated in the context of ECG classification. The network core reacts in 83ns to a stimulation and occupies a 0.21mm2silicon area.

To operate under severe energy constraints, clique-based neural networks are good candidates. They benefit from a reduced exchange of information between low-complexity processing units with no performance degradation. This paper proposes a modular, flexible and scalable architecture validated by an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With 0.8V power supply, 150nA unitary current and a low performance degradation, the neuron energy consumption is reduced to only 7fJ per synaptic event. The network occupies a 41,820μm2 silicon area.

Associative memories are data structures that allow retrieval of previously stored messages given part of their content. They, thus, behave similarly to the human brain's memory that is capable, for instance, of retrieving the end of a song, given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency (ratio of the number of bits stored to that of the bits used). Recently, a new family of sparse associative memories achieving almost optimal efficiency has been proposed. Their structure, relying on binary connections and neurons, induces a direct mapping between input messages and stored patterns. Nevertheless, it is well known that nonuniformity of the stored messages can lead to a dramatic decrease in performance. In this paper, we show the impact of nonuniformity on the performance of this recent model, and we exploit the structure of the model to improve its performance in practical applications, where data are not necessarily uniform. In order to approach the performance of networks with uniformly distributed messages presented in theoretical studies, twin neurons are introduced. To assess the adapted model, twin neurons are used with the real-world data to optimize power consumption of electronic circuits in practical test cases.

Encoded Neural Networks (ENN) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks' (HNN) for the same number of nodes. They are thus promising for implementing large scale neural networks mimicking the functioning of the human brain. The implementation of such a network on chip requires reducing the power consumption of the nodes to the femtojoule range to compare to human brain figures. Moreover, the circuit area must be reduced as much as possible. To address these challenges, this paper proposes a subthreshold analog ENN designed for the ST 65nm CMOS process. The designed circuit accepts power supply between 0.3V and 0.86V with currents below 300nA. In a network of 30 computation nodes, it yields a 32fJ energy consumption per decoding per node. The ENN converges only 21ns after being stimulated. Finally, the node core, i.e. without synapse, has a surface area of only 9.5µm2, and each synapse 3.6µm2.

Thanks to their brain-like properties, neural networks outperform traditional algorithms in certain group of applications. However, since they are wire-dominated systems, their hardware implementation poses numerous challenges as high latency and energy consumption. The recent technological improvements allow for stacking few dies one on another and designing 3D electronic circuits. This creates opportunities for 3D efficient implementations of neural networks targeting high-performance applications. This work explores the gains of 3D technology for neural networks relying on neural cliques. A general study shows up to 55% reduction in terms of total interconnect length and interconnect power consumption, and 74% reduction of the maximal interconnect delay. The proposed approach is validated with a power management applicative test-case. We demonstrate that, in this scenario, the 3D architecture reduces interconnect length and power by 35% and the maximal delay by 57%, compared to 2D.

Associative memories are data structures that allow retrieval of previously stored messages given part of their content. They thus behave similarly to human brain's memory that is capable for instance of retrieving the end of a song given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency (ratio of the number of bits stored to that of bits used). Nevertheless, it is well known that non-uniformity of the stored messages can lead to dramatic decrease in performance. Recently, a new family of sparse associative memories achieving almost-optimal efficiency has been proposed. Their structure induces a direct mapping between input messages and stored patterns. In this work, we show the impact of non-uniformity on the performance of this recent model and we exploit the structure of the model to introduce several strategies to allow for efficient storage of non-uniform messages. We show that a technique based on Huffman coding is the most efficient.

Encoded neural networks mix the principles of associative memories and error-correcting decoders. Their storage capacity has been shown to be much larger than Hopfield Neural Networks'. This paper introduces an analog implementation of this new type of network. The proposed circuit has been designed for the 1V supply ST CMOS 65nm process. It consumes 1165 times less energy than a digital equivalent circuit while being 2.7 times more efficient in terms of combined speed and surface.

Cortex codes are a family of block codes with good minimum distance properties whose parity-check matrices are very dense. Digital implementations of Cortex decoders using standard decoding algorithms have not shown an acceptable performance. Motivated by the encoder structure, a new bipartite graph is introduced and exemplified for the Cortex construction of the extended Hamming code. The Cortex graph has longer girth and approximately 80% less cycles than the Tanner graph. A Cortex and an LDPC-like decoder were implemented for the same code using identical PMOS-based Gilbert multipliers. This makes them the first reported analog decoders using mainly PMOS transistors. The Cortex outperforms the LDPC-like decoder in bit error rate and at the same time saves 44% of die surface. The results are supported using data from a test chip designed for a 0.25 mum CMOS process.

This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and reconfigurability. The architecture is applied to a DVB-RCS-like code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm20.25mum BiCMOS decoder can then decode any frame length from 40 up to 1824 bits