Layout parasitics can significantly affect the performance of analog integrated circuits (ICs). In this paper, a systematic method of optimizing an existing analog layout considering parasitics is presented for technology migration and performance retargeting. This method represents the locations of layout rectangle edges as variables and extracts circuit and layout integrity such as device symmetry, matching, and design rules as constraints. To ensure the desired circuit performance, bounds of layout parasitics are determined first. These bounds are used to constrain the layout geometries while retargeting existing high-quality layouts across technologies and specification sets. The problem is then solved by a graph-based algorithm combined with nonlinear optimization. The proposed method has been implemented in a parasitic-aware automatic layout optimization and retargeting tool (intellectual property reuse-based analog IC layout). Its efficiency and effectiveness are demonstrated by successfully retargeting operational amplifiers within 1 min of CPU time.

A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18 mum fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC decoder was implemented with about 8M transistors, placed on three tiers, each with one active layer and three metal layers, using 6.9 mm by 7.0 mm of die area. It was simulated to have a 2 Gbps throughput, and consume only 260 mW. This first large-scale 3D application-specific integrated circuit (ASIC) with fine-grain (5mum) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design tools. The 3D implementation is estimated to offer more than 10 xpower-delay-area product improvement over its corresponding 2D implementation. The work demonstrated the benefits of fine-grain 3D integration for interconnect-heavy very-large-scale digital ASIC implementation.

A 1024-bit, 1/2 -rate fully parallel low density parity check (LDPC) code decoder has been designed and implemented using a 3D 0.18/spl mu/m fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder with about 8M transistors was simulated to have a high throughput of 2Gb/s and a low power consumption of only 430mW using 6.4/spl mu/m by 6.3/spl mu/m of die area. The 3D implementation is estimated to offer more than 10/spl times/ power-delay-area product improvement over its corresponding 2D implementation. This first large-scale 3D ASIC with fine-grain (5/spl mu/m) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2D design flow combined with the needed 3D-design point tools.

Parasitic effects are extremely significant for the performance of analog and RF integrated circuits. Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements. In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints. Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. The algorithm has successfully retargeted operational amplifiers and an RF low-noise amplifier within minutes of CPU time.

The strong impact of layout intricacies on analog-circuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse-centric layout automation for CMOS analog blocks such as operational amplifiers. The layout-retargeting method first creates a template by extracting a set of constraints from an existing layout representation. From this template, new layouts are then generated corresponding to new technology processes and new device specifications. For large analog layouts, however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those emerging from layout symmetries. In this paper, we present a new method of multilevel symmetry-constraint generation by utilizing the inherent circuit structure and hierarchy information from the extracted netlist. The method has been implemented in a layout-retargeting system called Intellectual Property Reuse-based Analog IC Layout (IPRAIL) and demonstrated 18 times reduction in the number of symmetry constraints required for retargeting an analog-to-digital converter layout. This enables our retargeting engine to successfully handle the complexities associated with large analog layouts. While manual relayout is known to take weeks, our layout-retargeting tool generates the target layout in hours and achieves comparable electrical performance

Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated circuits. In order to ensure desired circuit performance, bounds on layout parasitics' magnitudes are determined first. Then, graph techniques are coupled with mathematical programming to constrain layout geometry based on these parasitic bounds. The algorithm has been demonstrated to ensure desired circuit performance during technology migration and performance specification changes.

Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance necessitates design reuse with special focus on layout aspects. This paper presents a computer-aided design tool and the methodology for a layout-centric reuse of large analog intellectual-property blocks. From an existing layout representation, an analog circuit is retargeted to different processes and performances; the corresponding correct-by-construction layouts are generated automatically and have performances comparable to manually crafted layouts. The tool and the methodology are validated on large analog intellectual-property blocks. While manual re-design and re-layout is known to take weeks to months, our reuse tool-suite achieves comparable performance in hours.