The performance analysis of maritime communication networks is frequently constrained by the widespread yet unrealistic assumption of a uniform spatial distribution of vessels. This paper presents a unified stochastic geometry framework that integrates high-fidelity physical channel models with nonhomogeneous vessel topologies to provide a more accurate analytical foundation. We first systematically demonstrate that the macroscopic geographical distribution of vessels is a dominant factor governing overall network performance, with significant performance variations observed across different deployment scenarios. Subsequently, to analyze the spatial origins of this performance, we introduce the coverage probability density function (Cpdf) as a novel metric. The Cpdf enables a finegrained spatial decomposition of the total coverage probability, thereby identifying key geographical areas that contribute most to network performance and quantifying the precise spatial impact of physical phenomena, such as multipath fading nulls. Our results affirm the primacy of realistic spatial modeling and provide a new analytical tool for the design and optimization of next-generation maritime networks.

This paper presents a novel concurrent fault simulation algorithm for nonlinear analog circuits. Between successive time steps in transient fault simulation, all faulty circuits in the fault list are simulated before the simulator proceeds to the next step. Four primary techniques, including fault grouping, fault ordering, state prediction, and reduced-order fault matrix computation, are proposed to significantly reduce analog fault simulation complexity by making use of the similarities between the faulty and fault-free circuits. The method has been implemented in a dc and transient fault simulator called CONCERT2, which is the first ever for nonlinear analog circuits. Up to two orders of magnitude speedup is obtained for complete transient fault simulation, without loss of accuracy in fault detection. It is shown that the methodology of CONCERT2 can significantly speed up the process of analog test stimulus generation.

Fast analog fault simulation is critical in test development and fault diagnosis for analog and mixed-signal circuits. It has been demonstrated that concurrent fault simulation methods can greatly reduce the computational complexity of analog fault simulation by sharing intermediate simulation results between different faults. In this paper we present an algorithm for dynamic fault grouping for transient fault simulation of nonlinear analog circuits. The goal of fault grouping in general is to minimize the total fault simulation running time for all faulty circuits while satisfying the simulation accuracy constraints. Fault grouping allows subset of faults with similar transient response characteristics to be simulated concurrently for a given test stimulus. Time step increments for each fault group are adaptively selected to limit simulation error while maximizing simulation concurrency. Results of simulation performance and statistics on test circuits are presented.

Dynamic transient tests can give better parametric and catastrophic fault coverage than both static DC and frequency domain AC tests in minimum test time. However determination of optimum transient tests is a complex search problem. Previous researchers have used accurate but computationally expensive fault simulation to guide the search for the optimum transient tests. In this paper we propose to use partial numerical simulation to guide the search for the optimum input test stimulus. The proposed method dynamically adjusts the number of Newton Raphson iterations and transient simulation time steps to perform fast test generation without sacrificing the test quality (fault coverage). This heuristic relies on the observation that although partial numerical circuit simulation may be inaccurate for determining the exact faulty circuit response to an applied test stimulus, it can determine very well how one test stimulus performs relative to another in detecting a fault. Simulation studies show that test generation using partial numerical simulation can generate high quality tests much faster compared to test generation methods based on accurate simulation without compromising test quality.

This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits.Three prima~techniques in CONCERT including fault ordering, state prediction, and rednced-order fault matrti computation, greatly simplifi fault sittudation by making use of the residual similarities bem'een the faul~andfault$ree circuits.Be~een successive time steps, all circuits in the fanlt list are simulated concurrently before the simulator proceeds to the nert titne step.CONCERT also generates accurate fault co~'erage statistics that are tied to the circuit specifications.Up to nt,o orders of magnitudes speedup are obtained for cotnplete fault simulation, )t'ithout any loss of accuracy.More speedup is achieved by COiVCERT for evaluating the fault coverase of a test, using fault ordering and fault dropping technique. AchowledgmentiThe author would like to tha~Ram&rishna Voor4aranam and Pramodchandran N Variyam for help and valuable discussions.

In this paper, we propose a novel test technique for fault detection and automated fault diagnosis using pole/zero analysis of embedded integrated passive. For pole/zero analysis, an ensemble of circuits obtained by perturbing the circuit under test parameters using their known statistical distributions is generated. The poles and zeros of every circuit in this ensemble are extracted. From knowledge of the passive circuit specifications, pass and fail regions for the critical poles and zeros are computed in the real-imaginary plane. The proposed test technique uses a region-matching algorithm to detect faults and perform automated diagnosis of catastrophic and parametric faults using frequency domain 2-port measurements.

In this paper we discuss the capabilities of the MiST PROFIT (Mixed Signal Test Program for Fault Insertion and Testing) software for hierarchical fault modeling, tolerance modeling, fault clustering and fault diagnosis of complex mixed-signal systems. The software is designed to exploit the relationships between high level system specifications and module-level faults in complex and nonlinear mixed signal systems. Hierarchical simulation based methods are used to capture fault effects at different levels of circuit abstraction. The key features of our approach are: (a) the ability to compute tolerance effects from nonlinear behavioral models at different levels of circuit design hierarchy accurately using low-cost simulation based methods, (b) the ability to perform compaction of fault effects while transferring fault effects from the leaf cells to the highest level behavioral models, (c) the ability to capture parametric (soft) failure effects over the entire anticipated range of faulty parameter values and (d) the ability to construct fault dictionaries given a set of least replaceable units to diagnose.