This paper addresses the problem of slack matching conditional asynchronous circuits for average-case performance. The behavior of the circuit is modeled using a Markov chain which governs switching between distinct modes of operations with potentially different performance requirements. Given the probability of mode switchings and desired cycle times for each mode, a minimum number of slack-matching buffers is inserted into the circuit such that an upper bound on the overall average cycle time is achieved. The problem is formulated as a Mixed Integer Linear Program and solved through relaxation. Experimental results on a new benchmark of circuits show a significant savings of slack matching buffers compared with the traditional approach and illuminate the type of circuits for which this new formulation is most beneficial.

An adaptive method to perform dynamic voltage and frequency scheduling (DVFS) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFS system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The technique, which can be realized with very simple hardware, is completely transparent to the application. The results of applying the method to some real application workloads demonstrate considerable power savings and fewer frequency updates compared to DVFS systems based on fixed update intervals.

Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of these extra circuits by take advantage of some compiler techniques. The compiler methods can be used innovatively to improve the synthesis results in terms of both power consumption and area, since these code motions lead to removing of completion detection and validity check parts of asynchronous designs. To the best of our knowledge this is the first effort in using the compiler pre-synthesis optimizations in asynchronous circuits to reduce the handshake overhead of these circuits in order to reduce the power consumption and area overhead. The approach is superimposed onto Persia synthesis toolset as a pre-synthesis source-to-source transformation phase, and the results show on average 22% and 24% improvement in terms of area and power consumption for asynchronous benchmarks, respectively.

We present a new method for implementing asynchronous FPGA logic cells which are configurable at pipeline level. Previous implementations of the basic elements of these logic cells were based on the pre-charged logic implementation which imposes some limitations on the size of the logic cell due to the stacking problem. To overcome this limitation we propose a novel method for implementing these templates. Our method uses standard single-rail computational circuits. It does not have any stacking problem and is not limited in size. The results show that a 4-input logic cell implemented by this method outperforms a previous 3-input logic cell by 16% in speed and 29% in power with a negligible area overhead.

Asynchronous circuits already have shown their benefits. The main drawback is the lack of powerful CAD and layout generation tools limiting the widespread use of the asynchronous methodology. QDI asynchronous circuits are known as a powerful category of asynchronous circuits targeting performance and power driven design. In this paper we addressed standard cell implementation of the template based QDI circuits utilizing standard layout generation tools. This is achieved by analyzing and removing outer cell isochronic fork constraint which is the main timing constraints limiting the standard layout generation. The isochronic fork free final netlist has 10--20% area overhead in average which is the cost of facilitating the use of standard CAD tools.

An efficient adaptive method to perform dynamic voltage and frequency management (DVFM) for minimizing the energy consumption of microprocessor chips is presented. Instead of using a fixed update interval, the proposed DVFM system makes use of adaptive update intervals for optimal frequency and voltage scheduling. The optimization enables the system to rapidly track the workload changes so as to meet soft real-time deadlines. The method, which is based on introducing the concept of an effective deadline, utilizes the correlation between consecutive values of the workload. In practice because the frequency and voltage update rates are dynamically set based on variable update interval lengths, voltage fluctuations on the power network are also minimized. The technique, which may be implemented by simple hardware and is completely transparent from the application, leads to power savings of up to 60% for highly correlated workloads compared to DVFM systems based on fixed update intervals.

This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implement a GALS circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.

This paper focuses on a clock generation scheme for implementation of GALS circuits on commercial FPGAs which are mostly synchronous. Previously overlooked timing problems of existing pausible clock generators are explored and a novel clock generator is introduced. To validate the proposed solution we implemented the clock generator and a simple port controller on FPGA. In addition, general design considerations to successfully implement a GALS circuit on FPGAs are discussed. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach can improve both power and performance of the system using different partitioning strategies.