Compact modeling of phase-locked loop (PLL) frequency synthesizer is proposed to reduce transient phase noise and jitter simulation time. Conventional small-signal noise assumption based frequency-domain simulation approach produces inaccurate results for nonlinear PLLs. Accurate analysis of nonlinear PLL are possible through time-domain, or transient noise simulation but time-domain simulation is computation-intensive and time-consuming. This paper presents a practical solution for transient phase noise and jitter analysis using compact modeling techniques. It features an autoregressive moving average process modeled voltage-controlled oscillator with fractional calculus and wavelet transform for phase noise decomposition and reconstruction, thereby reducing the phase noise and jitter simulation time to 25.8% of the transistor-level simulation with 0.4 dB @ 1 MHz phase noise error and 0.3 ps long-term jitter error for a 2 GHz PLL frequency synthesizer in a 65 nm CMOS process.

Compact model extraction of phase-locked loop (PLL) frequency synthesizer using system identification techniques is proposed to reduce post-layout simulation time. This is the first published compact model for PLL using system identification techniques. It features an autoregressive exogenous model for the charge pump and the loop filter with a lookup table for nonlinearity compensation and a radial basis function neural network for the voltage-controlled oscillator with nonlinear frequency-voltage relationship, thereby reducing the post-layout simulation time to 26% of the original circuits with the accuracy of 93%.

An asynchronous threshold detector for DC-960 MHz band impulse ultra-wideband (UWB) receiver is proposed in this paper. It features a DC power-free pulse discriminator. The proposed architecture in 90 nm CMOS achieves the lowest power consumption of 0.19 mW and energy consumption of 1.9 pJ/bit at 100 Mbps in the UWB receiver.