The sparsification of the reluctance matrix L-1 (where L denotes the usual inductance matrix L) has been widely used in several recent investigations to make the problem of simulation of interconnects tractable. Although these sparsification techniques work well in practice, the stability of these approximations has not been established, i.e., the sparsified reluctance and inductance matrices are not guaranteed to be positive-definite. In this work, we propose a band matching method that enjoys two advantages: First, we exploit the elegant structure of the inverse of banded matrices so as to construct an approximate inductance matrix L whose band entries match the band entries of original L, and whose inverse is a banded matrix. This approach yields a compact representation of both inductance and reluctance matrices. Second, we establish that the compact approximant L is guaranteed to be positive-definite. Simulation results show that our approach enjoys an approximation accuracy that is comparable to that of existing methods.

In this paper, we propose a metric for effective inductive coupling: the matrix (R + jωL)-1, where R and L are the resistance and inductance matrices. We use this metric to analyze the effectiveness of shields on reducing inductive coupling. Our analysis shows how the resistances of shields affect the effective inductive coupling between signal nets. SPICE simulations are carried out to validate the proposed metric.

The determination of the set (or window) of segments that are inductively coupled to a significant degree with a given segment plays a fundamental role in window-based techniques for the extraction of the susceptance of interconnect structures. We present a measure that quantifies the degree of coupling between segments in a window, thereby paving the way for an adaptive scheme for determining the coupling window associated with each segment. This measure has the properties that: (i)~it is well-correlated with the simulation error that is inherent in window-based susceptance extraction techniques, and (ii)~it can be computed efficiently using incremental and computation reuse techniques.

The authors present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L/sup -1/ matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent circuit by windowing the original inductance matrix. The resulting circuit model is sparse and exhibits the same stability property as the K method. Numerical results show that the proposed wire duplication model has high accuracy and is more efficient than many existing techniques.

We present a unified framework that considers flipflop and repeater insertion and the placement of flip-flop/repeater blocks during RT or higher level design. We introduce the concept of independent feasible regions in which flip-flops and repeaters can be inserted in an interconnect to satisfy both delay and cycle time constraints. Experimental results show that, with flip-flop insertion, we greatly increase the ability of interconnects to meet timing constraints. Our results also show that it is necessary to perform interconnect optimization at early design steps as the optimization will have even greater impact on the chip layout as feature size continually scales down.

In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L−1 matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent RLC circuit by windowing the original inductance matrix. The model avoids matrix inversions. Most important, it is more accurate and more efficient than many existing techniques.

In this paper we propose a new exact closed form mutual inductance equation for on-chip interconnects. We express the mutual inductance between two parallel rectangular conductors as a weighted sum of self-inductances. We do not place any restrictions on the alignment of the two parallel rectangular conductors. Moreover they could be co-planar or reside on different layers. Most important, experimental results show that our formula is numerically more stable than that derived by Hoer and Love (1965) for long parallel onchip interconnects.

In this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. The effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16-bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation.