A structure-independent method for space compaction in combinational circuits based on a new generic scheme is presented. It is shown that a single-output compactor can always be designed for compressing test responses of a circuit-under-test (CUT) with guaranteed zero-aliasing. Test responses from multiple outputs are compacted to a single periodic data stream. The compactor is independent of the fault model and can be designed only from the knowledge of the given test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic and almost all faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design can be accomplished without any information about the structure and functionality of the CUT, it would be useful for testing embedded cores as their internal structures may not be transparent to the users.

Presents the design of robust space compactors for reducing test data volume. These compactors are totally error-propagating for a given test test set, i.e. all possible errors are propagated irrespective of the fault model. In addition, these compactors also provide a high degree of error propagation for other test sets. All errors that affect up to three outputs of the circuit under test, as well as all errors that affect an odd number of outputs, are detected. This is irrespective of the test set or the fault model. The number of compactor outputs grows very slowly with the number of circuit outputs and size of the test set. Finally, no structural information of the circuit under test is required for fault simulation. We present experimental results on compactor design for a set of ISCAS and ITC-99 benchmark circuits.

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. In a general circuit, compaction of output space to a single output with zero-aliasing cannot always be achieved by earlier known approaches. In this work, it is shown that given a precomputed test set T, the test responses at the functional outputs of any arbitrary circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero aliasing. All the errors that are produced by T at the outputs of the CUT will also appear at the output of the compactor. The method is independent of the fault model and the structure of the CUT and uses only the knowledge of the test set T and the corresponding fault-free responses. A new concept of distinguishing outputs and a characteristic function is used to design the compactor. The test vectors in T are appropriately ordered to optimize the compactor logic, which to achieve zero-aliasing uses a test pattern counter to designate the sequence of test application and a special code checker. A design procedure is described to synthesize the compactor using logic synthesis tools, and relevant experimental results on hardware overhead for several benchmark circuits are presented. It is further shown that the overhead can be significantly reduced if the constraint of exact zero aliasing is slightly relaxed.

This paper addresses the problem of space compaction of test responses of combinational and scan-based sequential circuits. It is shown that given a precomputed test set T , the test responses at the functional outputs of the given circuit-under-test (CUT) can be compacted to a single periodic output, with guaranteed zero-aliasing. The method is independent of the fault model and the structure of the CUT, and uses only the knowledge of the test set T and the corresponding fault-free responses---it is particularly suitable for intellectual property (IP) cores. A new concept of distinguishing outputs and characteristic response function is utilized for synthesizing the compactor. Relevant experimental results on hardware overhead for several ISCAS circuits are presented. 1 Introduction Space compaction, which refers to the problem of reducing a wide data stream to a narrow signature stream, is commonly used for test response compression. Atypical space compaction scheme for a general c...

In this paper we propose a new method for the implementation of a self-dual circuit with alternating inputs. For every circuit output the self-dual complement is designed. Contrary to ordinary duplication and comparison the corresponding self-dual complements and the monitored circuit itself can be jointly, implemented. The self-dual duplicated circuits can be used in test mode, online mode and in fast mode without alternating inputs. Because of the necessary time redundancy, the approach is especially useful for online testing of control systems for which time is not critical.

Self-dual parity checking as a modification of ordinary parity checking is proposed in this paper. This method is based on the newly introduced concept of a self-dual complement of a given Boolean function. The parity prediction function f/sub p/ of ordinary parity checking is replaced by the self-dual complement /spl delta//sub p/ of this function such that the module-2 sum of the outputs of the monitored circuit and of /spl delta//sub p/ is an arbitrary self-dual Boolean function h. Because of the large number of possible choices for h as an arbitrary self-dual Boolean function, the area overhead for an optimal self-dual complement /spl delta//sub p/ is small. Alternating inputs are applied to the circuit; the output h is alternating as long as no error occurs. The fault coverage of this method is almost the same as for parity checking. The usefulness of the proposed method is demonstrated for MCNC benchmark circuits.