The C language, traditionally used in developing safety-critical systems, often faces memory management issues, leading to potential vulnerabilities. Rust emerges as a safer and secure alternative, aiming to mitigate these risks with its robust memory protection features, making it suitable for producing reliable code in critical environments, such as the automotive industry. This study proposes employing Rust code hardened by Control Flow Checking (CFC) in real-time embedded systems, which software is traditionally developed by Assembly and C languages. The methods have been implemented at the application level, i.e., in the Rust source code, to make them platform-agnostic. A methodology for leveraging the Rust advantages is presented, such as stronger security guarantees and modern features, to implement these methods more effectively. Highlighting a use case in the automotive sector, our research demonstrates the Rust capacity to enhance system reliability through CFC, especially against Random Hardware Faults. Two CFC algorithms from the literature, YACCA, and RACFED, have been implemented in the Rust language to assess their effectiveness, obtaining 46.5% Diagnostic Coverage for the YACCA method and 50.1% for RACFED. The proposed approach is aligned with functional safety standards, showcasing how Rust can balance safety requirements and cost considerations in industries reliant on software solutions for critical functionalities.

ShapeFuture will drive innovation in fundamental Electronic Components and Systems (ECS) that are essential for robust, powerful, fail-operational and integrated perception, cognition, AI-enabled decision making, resilient automation and computing, as well as communications, for highly automated vehicles. The overarching vision of ShapeFuture is to bring ECS Innovation to the heart of Europe’s Mobility Transformation, thereby elevating sovereignty by perfecting programmable ECS solutions for intelligent, safe, connected, and highly automated vehicles. In this paper, we detail not only the vision and mission of the ShapeFuture project, but we also showcase the results achieved during the first year.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Early identification of driving risks is crucial for driving safety. In this study, a deep learning method based on Long Short-term Memory (LSTM) with attention mechanism and XGBoost to recognize risk levels during driving simulation for early warnings, has been proposed. Here, we collected multimodal data -including driving data, eyes status, and basic physiological data-from driving simulators, eye trackers, and smartwatches for comprehensive analysis. By combining driving behavior and physiological features in each time window, the ability of LSTM networks was applied to analyze temporal features for prediction of the risk levels (Level 0, Level 1, and Level 2) in the next 20 seconds. Meanwhile, an attention mechanism was introduced to understand the importance of multiple features as well. Then the output of LSTM-attention was further refined using XGBoost, which demonstrated excellent performance in classification tasks. The integrated model showed that the overall accuracy achieved is above 89.97%, with an F1-score of 89.15%.

This paper presents a flexible Industrial Internet of Things (IIoT) infrastructure model, highlighting the integration of the Long Short-Term Memory (LSTM) algorithm for predictive analysis. A key component of this model is the Concentrator, a fog-computing local hub that provides a sandbox environment for third-party developments. Within this framework, clients can collect data using mechanisms provided by Original Equipment Manufacturers (OEMs), such as AROL Closure Systems, while independently developing proprietary algorithms. This approach eliminates the need for direct interaction with OEMs. The paper explores the use of the LSTM algorithm to develop a predictor for analyzing machine temperature behavior, allowing for the anticipation of potential faults.

This work in progress innovative practice paper intends to report on the outline and the ongoing progress of the EU-project GreenChips-EDU, which has been started in October 2023, and intends to fundamentally redesign educational microelectronics programs especially but not limited to students and professionals. One of the major goals is the design of a new microelectronics master program to which six European universities are contributing. The contents of this program will be substantially enhanced with green electronics contents innovative teaching methods. Other work will be done in the field of a new MBA program, self-standing modules for professionals, and a new microelectronics bachelor designed by one university of applied sciences.

This paper presents an approach to selectively implementing Software-Based Hardware Fault Tolerance techniques, focusing on control flow error detection. Selecting the most suited Control Flow Checking (CFC) algorithms can be challenging: the literature gives little guidance on the practical implementation in high-level programming languages. Instead, they propose implementations in low-level programming languages, e.g., Assembly. We implemented manually two established CFC algorithms in applications written in C programming language, automatically generated by the Model-Based Software Design approach, as usually done in the automotive industry. The purpose of this paper is to verify their effectiveness in such scenario, thanks to experimental results compliant with the ISO26262 automotive functional safety standard.

Development and verification of Advanced Driver Assistance Systems (ADAS) are challenging activities. Since ADAS have to deal with a huge number of possible operational situations happening in the real world and misbehavior can lead to high-severity hazards, it is imperative to test their behavior thoroughly. However, it is not cost-effective to reproduce all the possible operational situations in controlled environments (e.g., icy road, fog, very snowy steep road, ecc.) for testing ADAS through field test, i.e., through test vehicles, and it is unacceptable to demand the test to end-users. Moreover, discovering safety violations during field tests would lead to huge cost in terms of redesign and increased time-to-market, and it is therefore mandatory to anticipate this phase as early as possible. This can be achieved by means of an effective Hazard Analysis and Risk Assessment (HARA) as prescribed by the ISO26262, when the concept of the item, in our case the ADAS, is developed. Commonly recognized problems of this phase are repeatably and objectivity in terms of independence of its results from the involved engineers. This paper proposes an approach to perform HARA through clever use of vehicle-level simulators to test an initial specification of the ADAS behavior against simulated operational situations, considering also corner cases very difficult or too dangerous to be reproduced during field testing. As a proof-of-concept, the approach is applied to an Advanced Emergency Braking System (AEBS).

Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the Network-on-Chip (NoC) interconnect model to surpass the limitations imposed by traditional bus- or crossbar-based interconnection. This technology is also a promising solution for safety-critical industries where, primarily due to power and weight constraints, there is an increasing need in embedded systems for implementing multiple functionalities upon a single shared computing platform. This paper proposes a QoSinNoC framework, which is based on a set of quality of service (QoS) aware NoC architectures along with the analysis methodology including selected relevant metrics that enable an efficient trade-off between guarantees and overheads in mixed-criticality application scenarios. QoSinNoC architectures overcome the notion of strictly divided regions by allowing non-critical communication pass through the critical region, providing they do not utilize common router resources. This work aims to facilitate the usage of NoC technology by safety-critical industries such as avionics.

This paper presents a methodology to aid the development of multi-agent cyber-physical systems. The software architecture is structured in a multi-layer fashion, distributed on different devices (agents), making its design very challenging. A methodology is thus needed to meet the performance goal of such a system. The proposed methodology relies on Model-Based Software Design techniques, and on the Model/Software/Hardware-In-The-Loop (MIL, SIL, HIL) simulations. In particular, the HIL verification technique, which is widely adopted in the automotive and avionic industry also in the early development phases as a Computer-Aided Design tool, is the core tool of the real-time performances assessment verification. To speed-up the development process, and to obtain a toolchain coherent with the proposed approach, the adoption of a Model-Based Software Design methodology represents an optimal solution. Within those assumptions, we propose a benchmark of the methodology, applied on a customized multiagent system. The aim is to prove that the proposed method is able to achieve and verify a set of real-time requirements on the system behavior.

Some industrial domains, characterized by particularly strict safety standards - e.g., avionics - are facing issues when addressing the usage of commercial-off-the-shelf multi-processor system-on-chips and in particular new network-on-chip-based architectures. One key issue is related to the usage of such system-on-chips to implement mixed-criticality systems with the main goal of reducing size, weight, and power consumption of on-board equipment by reducing the number of computers moving from federated architectures based on singlecore processors to a single multi-core processor. To comply with relevant safety standards, a mixed-criticality system should be proven to enforce isolation among safety-critical and non-safetycritical tasks running on the multi-core hardware platform. This paper presents a software-level methodology tackling such issue. The proposed methodology exploits knowledge of the deterministic routing algorithm used by the network-on-chip to implement a safe and efficient partitioning of the system. This paper presents the software implementation and an experimental evaluation of the solution, proving its suitability for integration in an avionic application.

Modern avionics and space applications are characterized by increasing performance requirements. To satisfy such requirements, the use of commercial-off-the-shelf (COTS) multi-processor system-on-chips (MPSoCs) is a convenient solution. However, such systems are not developed for the avionic use case, therefore a validation approach is in order. In this paper, a validation approach is proposed for fault isolation, detection, and recovery mechanisms applied to mitigate fault effects in mixed-criticality systems. The approach is based on a combination of hardware-in-the-loop testing and fault injection techniques. Experimental results prove that the proposed approach does not interfere with the temporal behavior of the system under-test while allowing a realistic test of the software.

The Failure Mode, Effect and Diagnostic Analysis (FMEDA) is a technique widely adopted by automotive industry to assess the level of reliability of hardware designs. Although very useful, it has the problem of taking a long time to complete and requires experts with extensive knowledge of the circuit under consideration. In this paper, it is presented a comparison between the analysis results obtained from an automatic tool developed by the authors with respect to the ones obtained by hand from a team of experts, followed by a critical review of the strengths and weaknesses, about the rules for automatic classification of the faults effects.

Electronic control units have a central role in almost all the function of road vehicles. Some of these functions are safety critical so, during their development, it is requested by standards, like ISO 26262, to follow strict design rules and to perform in-depth verification steps. One of the technique recommended during the hardware design process is the failure mode, effect and diagnostic analysis (FMEDA). In industrial practice, this technique is manually applied by the designer by inspecting the circuit schematics, but in this way, the process is error-prone and make it difficult to take in proper consideration the contribution of the embedded software. In literature, it is possible to find some attempts to automate the FMEDA process. This article discusses a novel approach that allows reducing the time needed to perform FMEA and improving the quality of the achieved results.

Multi-processor system-on-chip (MPSoC) devices are a well known replacement of single-core devices. Some industries, like avionic, are particularly sensitive to the weight and power consumption. Such industries would really take advantage of reducing the number of computers by using MPSoCs. However, the usage of such devices in safety critical domain is currently more than limited. The main issue, which hinders the MPSoC usage in safety critical field, is the presence of on-chip resources shared by the cores. The interconnection itself is the most evident these shared resources. This aspect is an issue as it undermines the safety aspect of the system by providing non functional dependencies, especially from the timing point of view. The certification process is crucial in safety critical field and the system complexity makes the whole certification process harder and even unfeasible. The certification requires to prove that the system exhibits a precise set of guarantees to the safety-critical tasks. While the complexity was an issue for the well known bus-based MPSoCs, it becomes even more critical for the emerging network-on-chip (NoC) interconnection model. The QoSinNoC framework has been created to analyze a set of simple NoC architectures and the related techniques to enable their usage in the scope of mixed criticality. The main contribution of this work is an alternative routing algorithm which allows a better system utilization without any hardware modifications to the NoC architectures considered by QoSinNoC. Furthermore the framework has been upgraded with the power estimation feature which allows a better design space exploration.

In this IP session, there will be 3 presentations focusing on how to increase the in-field quality level of A/MS devices. The 1stpresentation will discuss using optical inspection data with electrical test data such that the combined data can be used to further screen out potentially bad devices that would have normally passed electrical testing. The 2ndpresentation discuses using a top level fault injection method to determine the ASIL levels in the ISO26262 standard. The 3rdpresentation will discuss the current progress of the P2427 Standardized Analogue Test Coverage Working Group and how this standard can be used to increase quality levels of A/MS devices.

The adoption of multi- and many-core processors in avionic applications is still limited by certification concerns, mainly due to non-deterministic behavior. In this paper, we review requirements of avionic applications, and we identify some of the critical issues that they are going to face on many-core processors. We then propose a preliminary version of a network-on-chip architecture suitable for airworthiness certification, which combines quality-of-service and fault-tolerance.

This article proposes a bounded interference method, based on statistical evaluations, for online detection and tolerance of any fault capable of causing a deadline miss. The proposed method requires data that can be gathered during the profiling and worst-case execution time (WCET) analysis phase. This article describes the method, its application, and then it presents an avionic mixed-criticality use case for experimental evaluation, considering both dual-core and quad-core platforms. Results show that faults that can cause a timing violation are correctly identified while other faults that do not introduce a significant temporal interference can be tolerated to avoid high recovery overheads.

Multi-core is a game changer for automotive industry, providing unprecedented computing capabilities, and allowing consolidating heterogeneous applications into a single device with benefits in terms of cost and reuse. Multi-core asks for virtualization of applications, moving from the hardware-centric perspective to the function-centric perspective: applications on a single electronic control unit (ECU) are transformed into hardware-agnostic functionalities that hosted by multicore ECUs alongside other, unrelated, applications. Moreover, to exploit multi-cores to the full extent in some automotive applications, the guarantee is needed that different applications exposing different criticalities (e.g., ISO26262 ASIL D and ISO26262 ASIL B) can coexist. The paper presents the technologies available to support these concepts such as AUTOSAR and embedded virtualizations, presenting the main issues that have to be solved and discussing the state of the art.

High compression ratio is crucial to cope with the large amounts of data produced by telemetry sensors and the limited transmission bandwidth typical of space applications. A new generation of telemetry units is under development, based on Commercial Off-The-Shelf (COTS) components that may be subject to misbehaviors due to radiation-induced soft errors. The purpose of this paper is to study the impact of soft errors on different configurations of a discrete cosine transform (DCT)-based compression algorithm. This work's main contribution lies in providing some design guidelines.

In this paper a novel technique is proposed for online detection of timing interference in multicore architectures. The technique is aimed at mixed-criticality workloads. This paper describes a method to use hardware performance counters to detect such misbehaviors. Experimental data is gathered, showing the viability of this method. The method can be used as safety-net in several scheduling approaches.

The paper proposes a novel hybrid architecture to consolidate avionic applications with different levels of criticality in a multicore processor. The architecture stems from the need of deploying into one computer different applications with conflicting requirements in terms of criticalities that today are mapped into multiple independent computers. The architecture relies on a type-1 hypervisor to separate the applications exposing different criticalities levels, to avoid that low-criticality applications might corrupt high-criticality applications. Moreover, the architecture exploits custom-designed hardware watchdogs to enforce error detection. Fault-injection results are presented to illustrate the robustness of the architecture.

In recent years, use of FPGAs has been gaining more momentum for space applications as there are cases where using them can significantly reduce developments costs and time. In order to ensure correct operation in space, they have to be rad-hard, but most of such components are subject to ITAR. Atmel is the only provider for ITAR-free rad-hard FPGAs, but the default development flow provided leaves much to be desired. The contribution of this work is two-fold: First of all, we present a fully automated flow which improves the usability of the default development flow provided by Atmel, while requiring only a bare minimum of configuration for each design. Secondly, we show how to extend this flow in order to integrate external programs which can be used as in-place substitutions of steps of the default flow. Our experiments show that the proposed flow can significantly boost both the productivity of the designers and the QoR of the final implementations.

Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures are needed. In this paper we present an in-depth experimental evaluation of a hybrid architecture to detect transient faults affecting microprocessors. The architecture leverages an hypervisor-based task-level redundancy scheme that operates in conjunction with a custom-developed hardware module. The experimental evaluation shows that our lightweight redundancy scheme is able to effectively cope with malicious faults as those affecting the pipeline of a RISC microprocessor.

Commercial-off-the-shelf (COTS) components are crucial for the success of future space missions as, although not being specifically designed for space, they are the only components able to meet the performance requirement that new missions impose to designers. COTS memories are particularly appealing as large memory arrays can be implemented, which can be made immune to radiations by means of cost-effective information redundancy schemes. In this paper, we present an intellectual property (IP) core implementing a (12, 8) Reed-Solomon (RS) code for error mitigation that is suitable for COTS Flash NAND and NOR memories. The main novelty of the proposed scheme consists in its architecture which is based on a shortened Reed-Solomon code with a fast error detection feature. Two implementations have been studied: a fully combinational scheme that provides error detection and correction in the access cycle and a two-stage pipeline with early (in-cycle) error detection a 1-cycle latency correction. The pipelined version presents the specific advantages of minimizing the time penalty associated to a traditional RS implementation. We have characterized the area and timing performance of the proposed architectures in a variety of FPGA implementations, obtaining a maximum frequency of 47 MHz for the combinational implementation and 53 MHz for the pipelined one (in a Virtex 6 FPGA), with a quick 5 ns error detection. In addition, we have characterized the fault resiliency of the proposed schemes with respect to Single Event Transients and Single Event Faults.

This paper presents an enhanced design flow for the implementation of hardened systems on SRAM-based FPGAs, able to cope with the occurrence of Single Event Upsets (SEUs). The framework integrates three strategies independently designed to tackle the problem of SEUs; first a systematic methodology is used to harden the circuit exploiting an enhanced TMR-based technique, coupled with partial dynamic reconfiguration. Then, a robustness analysis is performed to identify possible TMR failures, eventually solved by a specific local re-design of the critical portions of the implementation. We present the overall flow and the benefits of the solution, experimentally evaluated on a realistic circuit.

In this paper we present a new software framework to analyze and modify circuits netlists in an automatic fashion. We developed an API that implements low-level functionalities above which it is possible to create complex algorithms. We then developed a second software layer to implement hardening techniques for Single Event Effects (SEEs) in digital microcircuits. Experimental results prove the effectiveness of the automatic introduction of mitigation techniques.

To cope with the ever-growing demand for computing power, the space community is working for introducing Commercial-Off-The-Shelf (COTS) components in future space missions. As COTS components are not designed for working in such a hostile environment like space, suitable fault detection, isolation and recovery strategies are needed to guarantee the dependability of the system using COTS components, along with a part selection procedure to assure the proper level of quality. This paper describes a framework to automate the generation of a reliable architecture for data handling computers for space applications.

The higher resiliency of Flash-based FPGAs to Single Event Upsets (SEUs) with respect to other non radiation-hardened devices, such as SRAM-based FPGAs, are increasing more and more their demand for avionic and space applications, where a harsh environment rich in ionizing radiation has to be faced. In this type of devices other transient faults tend to dominate over SEUs, especially when the device operates at high frequency. In this scenario, it is expected that Single Event Transient (SET) faults will predominate. As a result, designers will still need prediction techniques to forecast the effects of ionizing radiation in their designs. Although radiation testing is a feasible method for evaluating circuit sensitiveness against SETs, it is hard to implement, very expensive, and it can be used only in later phases of the design process, when a prototype of the system is available. On the other hand, simulation techniques need a first technology characterization step and also require a very detailed model for being effective; moreover they are application dependent. In this paper we propose a new software tool for analyzing designs implemented in Flash-based FPGAs and estimating SET sensitiveness. The evaluation process is static, as it does not entail any simulation. In particular, it provides worst-case results, thus being intrinsically more conservative than other dynamic methods. Experimental results are presented comparing the ones coming from radiation testing and the results provided by the presented tool. They validate the proposed approach.

The design of complex embedded systems deployed in safety-critical or mission-critical applications mandates the availability of methods to validate the system dependability across the whole design flow. In this article we introduce a fault injection approach, based on loadable kernel modules and running under the Linux operating system, which can be adopted as soon as a running prototype of the systems is available. Moreover, for the purpose of decoupling dependability analysis from hardware availability, we also propose the adoption of hardware virtualization. Extensive experimental results show that statistical analysis made on top of virtual prototypes are in good agreement with the information disclosed by fault detection trends of real platforms, even under real-time constraints.

Flash-based FPGAs are increasingly demanded in safety critical fields, in particular space and avionic ones, due to their non-volatile configuration memory. Although they are almost immune to permanent loss of the configuration data, they are composed of floating gate based switches that can suffer transient effects if hit by high energetic particles with critical consequences on the implemented logic. This paper presents a new way for the analysis of the impact of single event effects in flash-based FPGAs. We proposed a new methodology to identify the most critical switches inside the configuration logic block and the most redundant and robust configuration selection for each logic function. The experimental results achieved by fault injection demonstrated the feasibility of the proposed method and show that by using the most robust functional mapping it is possible to enhance the reliability of the entire design with respect to a not robust ones.

The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (Systems on Programmable Chip, or SoPCs). When deployed in safety- or mission-critical applications, as avionic- and space-oriented ones, Singe Event Effects (SEEs) affecting COTS FPGA, which may have catastrophic effects if neglected, have to be considered and SEE mitigation techniques have to be employed. In this paper we explore the adoption of known techniques (such as lockstep, checkpointing and rollback recovery) for SEE mitigation to processors cores embedded in SoPCs, and propose their customization, specifically addressing the characteristics of programmable devices. Since the resulting design flow can easily be supported by automation tools, its adoption is particularly suitable to reduce the design and validation costs. Experimental results show the effectiveness of the proposed approach when compared to conventional TMR-based solutions.

The paper presents the development of three different analysis methodologies in order to evaluate soft errors effects in flash-based FPGAs. They are complementary and can be used in different design stages, from the device characterization up to the design sensitiveness estimation. First results are very promising, proving that such methodologies are valid and open new ways of investigation. In particular, we are going to upgrade the experimental setup in order to support higher frequencies (up to 250 MHz) for further characterizing SEE effects. Moreover, a benchmark circuit should be defined in order to correctly predict the expected number of SETs for real circuits, taking into account other side effects, like broadening and logical masking. We expect that from the analysis results we will able to delight suitable hardening techniques that will undergo to both radiation test and prediction analysis.

Radiation-hardened-by-design (RHBD) SRAM-based FPGAs will play a crucial role in providing new generations of satellites with reliable in-flight reconfiguration ability, which is mandatory to enable the successful use of configurable computing in space. RHBD SRAM-based FPGAs sensitiveness against ionizing radiation is normally evaluated resorting to radiation testing, which provides the device cross-section. However, as a matter of fact, applications implemented on such devices use only a portion of the available resources, and the corresponding configuration memory. As a result, application-oriented sensitiveness analysis tools are needed that, by analyzing how the FPGA resources are actually used by a given application, produce application cross-section that is a reliability figure more accurate than device cross section. This paper presents a novel application-oriented sensitiveness analysis tool we are developing for the new generation of SRAM-based FPGAs from Atmel: the ATF280E.

The space community is showing a growing interest for shifting from designs based on fully-custom components to a more cost- and time-effective approach based on commercial off the shelf components. As a result, there is a growing need for methods to develop quickly reliable on-board electronic systems that meet reliability constraints typical of space-oriented applications. The purpose of this paper is to present an approach for developing Linux-based on-board computers for data handling serving as building blocks for low-cost scientific satellites. The approach is based on a scalable technique that mixes hardware and software error detection techniques to balance implementation cost with dependability.

Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing tuning known mitigation techniques accordingly. Radiation experiments results are presented and commented demonstrating that the proposed methodology is a viable solution to measure the transient pulses width.

SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory. SEUs may have critical effects on the circuit FPGA devices implement. In order to deploy safety- or mission-critical applications on SRAM-based FPGAs, designers need to adopt hardening techniques, as well as methodologies for estimating and validating the SEU's sensitivity of the obtained applications in the early design phase. In this paper we describe a new methodology for predict the effects of SEUs by combining static and dynamic analysis of the circuit's FPGA implements. The proposed methodology is able to identify the critical single event upset locations within the configuration memory and to provide a detailed classification of the provoked effects. Experimental results on several realistic applications demonstrate the feasibility of the proposed methodology.

Nowadays Field Programmable Gate Arrays (FPGAs) are an improved technology for developing high-performance embedded systems. SRAM-based FPGAs offers the possibility of in-the-field reconfiguration that results in the ability to adapt the product to modified user's requirements, to enrich the product's features, or simply to correct bugs. With the advent of multi-million gate FPGAs, the size of the configuration information that defines what circuit the FPGA implements has increased drastically, and thus the amount of external memory needed to keep the configuration data is increasing dramatically. In this work we developed a novel configuration compression system that exploits internal configuration mechanism of modern SRAM-based FPGAs and results in high compression efficiency. The proposed system is applicable to any modern SRAM-based FPGA devices having an embedded microprocessor core since the configuration data are processed as raw data. Moreover, the proposed approach does not require any external hardware support and allows high speed dynamic reconfiguration. Experimental results on Xilinx SRAM-based FPGAs platform implementing several real-world circuits demonstrated 82% savings in memory on the average.

DNA microarray technologies are an essential part of modern biomedical research. The analysis of DNA microarray images allows the identification of gene expressions in order to drawn biologically meaningful conclusions for applications that ranges from the genetic profiling to the diagnosis of oncology diseases. Unfortunately, DNA microarray technology has a high variation of data quality. Therefore, in order to obtain reliable results, complex and extensive image analysis algorithms should be applied before actual DNA microarray information can be used for biomedical purpose. In this paper, we present a novel hardware acceleration architecture specifically designed to process DNA microarray images. The proposed architecture uses several units working in a single instruction-multiple data fashion managed by a microprocessor core. An FPGA-based prototypal implementation of the developed architecture is presented. Experimental results on several realistic DNA microarray images show a reduction of the computation time of one order of magnitude if compared with previously developed software-based approach.

This paper shows how the use of exhaustive fault injection campaigns in conjunction with the analysis of the property of a circuit, allows to improve the efficiency of the checker of self checking circuits. Experimental results coming from fault injection campaigns on a Reed-Solomon decoder demonstrated that by observing the occurred errors and the correspondent detection module has been possible to reduce the number of detection module, while paying a small reduction of the percentage of SEUs that can be detected.

Systems-on-programmable-chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a Web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack

Automotive systems embed several electronic control units whose purpose is to help drivers in controlling vehicles, as well as guaranteeing the safety of vehicles' occupants. The occurrence of faults affecting these units can have dramatic impacts, and must be forecasted as earlier as possible during the conception of new vehicles. In this paper we propose a new fault-injection system based on a hardware-in-the-loop vehicle model. The main novelty of our system is the possibility of directly relating fault effects to vehicle's dynamic response without performing long and expensive experiments on a prototype running on a test track

Reconfigurable compute fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety- or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced by transient faults within the resources of an RCF Motorola MRC6011 and we resorted to extensive fault injection to investigate the effects of transient faults

Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique

In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems' dependability more difficult than ever. In this paper we present a new approach to detect control-flow errors by exploiting a low-cost infrastructure intellectual property (I-IP) core that works in cooperation with software-based techniques. The proposed approach is particularly suited when the system to be hardened is implemented as a system-on-chip (SoC), since the I-IP can be added easily and it is independent on the application. Experimental results are reported showing the effectiveness of the proposed approach.

The very high integration levels reached by SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence rate of single event upsets (SEUs) in their configuration memory, which can produce multiple errors affecting routing resources. Based on detailed analysis of this phenomenon, we devised a reliability-oriented place and route algorithm able to significantly improve the reliability of SRAM-based FPGAs with limited costs in terms of performance degradation and resource occupation. To evaluate the effectiveness of the algorithm we performed extensive fault injection experiments.

Checking if microprocessor cores are fully functional at the end of the productive process has become a major issue. Traditional functional approaches are not sufficient when considering modern designs. This paper describes new improvements for an existing evolutionary algorithm, called µGP, able to generate Turing-complete programs; these are exploited, along with hardware acceleration techniques, to add content to a qualifying test campaign by automatically generating assembly programs. The approach is suitable for medium-sized processor cores. The experimental evaluation performed on a SPARCv8 clearly shows the potentiality of the approach, and the effectiveness of the enhancements to the evolutionary core.

SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to single event upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs' configuration memory. In this paper we propose a new method for assessing the impact of faults in the configuration memory on the FPGA dependability. The method uses static analysis, thus reducing greatly the time for performing dependability evaluation.

This paper suggests a framework to examine, evaluate and characterize an evolutionary test-program generation problem. The methodology exploits the definition of distance functions at the genotypic and phenotypic levels to perform a local analysis of an unknown space. A hardware accelerator device is used for speeding up test-program evaluations. A complex microprocessor was used as case study. Experiments show how the local analysis allowed discovering several characteristics of the task and foreseeing the behavior of the test-program generation.

This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.

Microprocessor soft cores offer today an effective solution to the problem of rapidly developing new system-on-a-chips. However, all the features they offer are rarely used in embedded applications, and thus designers are often involved in the challenging task of soft-core customization to obtain application-specific processors. Suitable input stimuli are automatically generated while reasoning only on the software application the processor is intended to execute, while all the details concerning the processor hardware are neglected. Experimental results on an 8051 soft core show the effectiveness of the proposed approach.

In this paper we present a concurrent error detection (CED) technique that can be applied to behavioral RTL models of data dominated systems. The technique obtains CED through duplication of operations with shifted operands. Duplication is performed according to transformation rules that can automatically be applied to a behavioral model. Preliminary experimental results show the viability of the proposed technique.

Single event transients (SETs) on combinational gates are becoming an issue in deep sub-micron technologies, thus efficient and accurate techniques for assessing their impact are strongly required. This paper presents a new technique that embeds time-related information in the topology of the analyzed circuit, allowing evaluating the effects of SETs via zero-delay simulation instead of timed simulation. The analysis of complex designs becomes thus possible at a very limited cost in terms of CPU time. The paper reports results showing how the proposed method can be effectively used to analyze complex designs.

Commercial-off-the-shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory. The method combines radiation testing for technology characterization and simulation-based fault injection for SEU propagation. Experimental results we gathered with the purpose of modeling the effects of SEUs in the FPGA configuration memory are reported and commented.

This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.

In this paper we propose an approach to speed-up fault injection campaigns for the evaluation of dependability properties of processor-based systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.

This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

Testing is a crucial issue in SOC development and production process. A popular solution for SOCs that include microprocessor cores is based on making them execute a test program. Thus, implementing a very attractive BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor. The method can be partially automated and combines ideas from traditional functional approaches and from the ATPG field. We assess the feasibility and effectiveness of the method by applying it to a 8051 core.

The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at every step of the design cycle. In this paper, we describe how fault injection techniques have been integrated in an existing co-design tool and which advantages come from the availability of such an enhanced tool. The effectiveness of the proposed tool is assessed on a simple case study.

The current digital systems design trend is quickly moving toward a design-and-reuse paradigm. In particular, intellectual property cores are becoming widely used. Since the cores are usually provided as encrypted gate-level netlist, they raise several testability problems. The authors propose an automatic approach targeting processor cores that, by resorting to genetic algorithms, computes a test program able to attain high fault coverage figures. Preliminary results are reported to assess the effectiveness of our approach with respect to a random approach.

In the last decade, researchers devoted much effort to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application, circuits are subjected to an activity level higher than the normal one: the extra power consumption due to test application may thus cause severe hazards to circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered. In this paper we propose an algorithm to design a test pattern generator based on cellular automata for testing combinational circuits that effectively reduces power consumption while attaining high fault coverage. Experimental results show that our approach reduces the power consumed during test by 34% on average, without affecting fault coverage, test length and area overhead.

Tools for evaluating the worst-case peak power consumption of sequential circuits are highly useful to designers of low-power circuits. Previously proposed methods search for the initial state and the couple of vectors with maximum consumption, without fully considering the reachability of the initial state. This paper shows that this approach can lead to a significant underestimation of the maximum peak power consumption and proposes a new algorithm that overcomes this drawback. Experimental results show that for many circuits the algorithm is able to provide better results than those known up to now, while an approximate version is able to deal even with the largest benchmark circuits.

Combining different techniques for sequential automated test pattern generation (ATPG) can help overcome their respective limits and exploit their advantages. In this paper, a hybrid technique resulting from mixing topologic and symbolic approaches to the sequential ATPG problem is presented. Macros are first identified within the circuit (possibly resorting to RT-level knowledge of circuit architecture). Information about macro behavior is then computed and efficiently stored resorting to symbolic techniques. A topological tool exploits this information during the ATPG process to speed-up the propagation task and to identify early unsuccessful choices. Experimental results are reported, demonstrating that the method is able to improve the efficiency of a topological ATPG in terms of required CPU time and attained fault coverage, especially on medium-sized control-dominated circuits.

Partial scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several techniques for flip-flop selection based on structural analysis have been presented in the literature. In this paper we first propose a new testability measure based on the analysis of the circuit State Transition Graph (STG) through symbolic techniques. We then describe a scan flip flop selection algorithm exploiting this measure. We resort to the identification of several circuit macros to address large sequential circuits. When compared to other techniques, our approach shows good results, especially when it is used to optimize a set of flip-flops previously selected by means of structural analysis.

The constantly increasing circuit size makes the sequential ATPG problem a challenging area even when simulation-based algorithms are exploited. Several techniques have been proposed which mainly resort to logic simulation, reverting to fault simulation only when strictly required. In this paper we present a new Genetic Algorithm-based test generation method which exploits information coming from a logic simulator (e.g., the circuit activity and the reached states) to guide the search process, in particular in the fault excitation phase. Experimental results show the effectiveness of the proposed method when compared with other Genetic Algorithm-based test generators.