Process variability effects and subtle defect mechanisms in deeply scaled analog/mixed-signal/RF (AMS) silicon technologies combine in malicious ways to increase DPPMs of mixed-signal Systems-on-Chips (SoCs). This has driven the need to increase defect coverage while minimizing testing costs. However, testing embedded AMS components in mixed-signal SoCs has always been a challenge due to test access limitations and requirement for labeled data. In this work, we focus on eliminating the requirement for labeled data. As such, rather than measuring the specification values of embedded AMS components, it is more expedient to devise tests using on- chip resources along with low cost mechanisms for identifying outlier behaviors in measured data to identify devices with parametric and catastrophic defects. To resolve this, what is needed are : (a) a test generation methodology that separates outlier from inlier device behaviors making them easily detectable and (b) a response analysis approach that can draw boundaries between multi-dimensional "good" and "outlier" behaviors with such computational ease that it can be invoked in each test generation iteration to quantify the quality of the test being considered. In this context, a novel test stimulus generation approach using clustering of test data in hyperdimensional spaces is developed that maximizes the similarities of inlier devices in the hyperdimensional space thereby allowing outlier devices to be identified easily by their corresponding hypervector representations from their dissimilarity with hypervectors of inlier devices. Such an approach overcomes the major drawback of prior approaches by eliminating the requirement for labeled data. For decision-making, a one-class hyperdimensional classifier that relies on a single cluster boundary (as opposed to complex boundaries in nonlinear spaces), is used to separate "good" vs. "bad" devices. The classifier is computationally efficient, outperforms existing techniques for defect coverage, and drives the search for the optimal test stimulus. Simulation results on test circuits prove the benefits of the proposed approach over prior testing methods.

Testing challenges of soft failures, including transient and intermittent failures, are being compounded by the fact that these failures are often induced by interference from time-varying stress factors, especially under a harsh environment in safety-critical applications. This paper presents a predictive analytics methodology using a continuing stream of anomaly data to tackle soft failure testing challenges. It is within a proposed silicon health prognosis framework. Multi-State Models (MSM) are applied to model soft failure progression with prognostic factors (e.g. interference) as time-varying covariates. The unique power of anomaly data can be unleashed with statistical machine learning techniques to infer potential interference effects on failure evolution and recovery rates. Failure prediction results can further be used for safety mitigation decision making. Several examples in context of 3-D mixed-signal SOC are analyzed to illustrate the proposed method. These predictive analytics methodology and prognosis framework are expected to pave an alternative way to improve dependability of safety-critical systems.

Freedom from Interference (FFI) is one of the critical criteria to support coexistence of elements with different criticality in a mixed-criticality system (MCS). The principle of FFI is to ensure an element with lower criticality cannot influence an element with higher criticality. Existing FFI analysis solutions mainly focus on product development phase, and most are qualitative methods. They were inefficient to provide a comprehensive coverage of trouble spots due to wide environmental or usage model variations in many applications. They were also difficult to differentiate cascading effect from common-source effect. In this paper we propose a causal learning method based upon mining in-field anomaly data, which have embodied rich real-life information, to verify FFI. It is expected to address the aforementioned challenges, providing a new way to identify interference issues.

Safety is a critical objective for automotive developments. Functional Safety of automotive analog and mixed-signal circuits faces several challenges; on the other hand, analog behavior provides an opportunity for early anomaly alert, thus improving functional safety. In this paper we propose a machine learning based methodology using data-driven anomaly detection for analog automotive circuits. The contribution of this work is to provide a framework of mining the dynamic in-field time series data in the context of system operation to detect anomalous events from analog functional safety perspective, with minimal hardware overhead. We present a realistic example to illustrate and analyze the proposed method. It presents an approach for improving functional safety of analog circuits in automotive applications.

In this IP session, there will be 3 presentations focusing on functional testing and fault injection for automotive functional safety applications as well as a discussion on fault simulation and modeling for relevant analog test content. The 1stpresentation will discuss verification solutions that accelerate fault injection for diagnostic coverage to meet ASIL requirements. The 2ndpresentation discusses the use of focused random testing to achieve better functional coverage for automotive products. The 3rdpresentation will discuss the various challenges associated with analog fault coverage in the absence of standards and discusses approaches to address them.

Start of the above-titled section of the conference proceedings record.

A practical fault simulation methodology for analog circuits in mixed-signal designs is presented. The methodology leverages the mixed-signal simulation environment of a product and performs mixed-signal fault simulation of embedded analog circuits. A set of open-circuit and short-circuit faults are extracted with guidance from layout parasitics, and automatically injected in to the net list. Fault coverage of manufacturing tests on faults in the transmitter of a high speed serial interface design are reported with two different observation criteria. Results indicate the amount of test reduction that can be achieved and the importance of appropriate observation in fault detection.

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.

Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.

In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem eve get a test set with optimal fault coverage and fault separation.

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

In this work we present a behavioral fault simulation technique for mixed-signal ICs, wherein a robust function approximation method namely regression splines are applied to automatically extract behavioral block parameters. The use of these robust high-level functions enables true behavioral fault simulation while preserving the statistical dependence on the process tolerance. We demonstrate significant speed-up over traditional Monte Carlo methods for two typical mixed-signal circuits, a sigma-delta modulator and a PLL.