For future exascale computing systems, ultra-high-density memories would be required that consume low power to process massive data. Of the various memory devices, 3D-stacked DRAMs using TSVs are a perfect solution for this purposes. In addition to providing high capacity, these provide functional flexibility to the computing system by attaching a logic die in each 3D-stacked DRAM chip. However, the high capacity 3D-stacked DRAMs suffer from a significant loss of refresh power, which is solely required to maintain data. Although various schemes have been proposed to mitigate this issue, they cannot be adopted by commercial products due to compatibility issues. To tackle this issue, we propose EXTREME, which effectively reduces the refresh power of 3D-Stacked DRAMs. In order to retain the compatibility with OS, a simple page table manager is implemented at the logic die of 3D-stacked DRAM devices, which pins the page table to a specific memory space. The experiment results demonstrate that this reduces the refresh power at idle time by up to 98 percent with 16 KB of SRAM (static RAM) and 64 KB of DRAM register overhead for a 2 GB 3D-stacked DRAM device.

A table look-up model for MOSFETs has been implemented into SPICE2G.6 to compute I/sub ds/ and its first-order derivatives using a three-dimensional linear isoparametric shape function. This method accurately calculates continuous and monotonic I/sub ds/ and its continuous first-order derivatives with a relatively small number of data points. As a consequence, this table look-up model converges more rapidly, compared to the analytic model of SPICE2G.6. The total number of Newton-Raphson iterations is on the average 10% less than that of SPICE2G.6 simulation.>