Demo Data from VLDB 2026 / reviewers in the wild / expert
Anthony Jayakumar
dblp:45/5604
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 3Computer networks · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 51% Integrated circuit design · 28% Parallel and multicore computing · 16% | |
| Artificial intelligence
1 paper |
Learning paradigms · 100% | |
| Theoretical computer science
1 paper |
Mathematical optimization · 100% |
Topics — the 11 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures › machine learning accelerator
neural network accelerator |
0.0 | 2 | 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks · NIPS 1992 Experimental Evaluation of Learning in a Neural Microsystem · NIPS 1991 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
analog VLSI neural network |
0.0 | 1 | 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks · NIPS 1992 |
Parallel and multicore computing › parallel computing › parallel machine learning
parallel training |
0.0 | 1 | 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks · NIPS 1992 |
Machine learning › Learning paradigms
supervised learning |
0.0 | 1 | 1990 | Relaxation Networks for Large Supervised Learning Problems · NIPS 1990 |
Integrated circuit design › digital circuit design
CMOS circuit design |
0.0 | 1 | 1988 | A 16×16 crosspoint switch for ternary encoded signals · IEEE J. Sel. Areas Commun. 1988 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks · NIPS 1992 |
Integrated circuit design › analog and mixed-signal circuits
analog VLSI |
0.0 | 1 | 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks · NIPS 1992 |
Hardware accelerators and domain-specific architectures › neural network hardware
analog neural network hardware |
0.0 | 1 | 1991 | Experimental Evaluation of Learning in a Neural Microsystem · NIPS 1991 |
Emerging computing paradigms
neuromorphic computing |
0.0 | 1 | 1991 | Experimental Evaluation of Learning in a Neural Microsystem · NIPS 1991 |
Mathematical optimization
continuous optimization |
0.0 | 1 | 1990 | Relaxation Networks for Large Supervised Learning Problems · NIPS 1990 |
Physical-layer communications › modulation
line coding |
0.0 | 1 | 1988 | A 16×16 crosspoint switch for ternary encoded signals · IEEE J. Sel. Areas Commun. 1988 |
Methods — techniques the papers use, named apart from their topics
relaxation · 0.0CMOS fabrication · 0.0gradient descent · 0.0learning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | A Parallel Gradient Descent Method for Learning in Analog VLSI Neural Networks
Joshua Alspector, Ron Meir, Ben P. Yuhas, Anthony Jayakumar, D. Lippe |
NIPS | 4 |
| 1991 | Experimental Evaluation of Learning in a Neural Microsystem
Joshua Alspector, Anthony Jayakumar, Stephan Luna |
NIPS | 2 |
| 1990 | Relaxation Networks for Large Supervised Learning Problems
Joshua Alspector, Robert B. Allen, Anthony Jayakumar, Torsten Zeppenfeld, Ron Meir |
NIPS | 3 |
| 1988 | A 16×16 crosspoint switch for ternary encoded signalsabstractA crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3- mu m CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm/sup 2/.> Anthony Jayakumar, Kenneth C. Young Jr. |
IEEE J. Sel. Areas Commun. | 1 |