The paper describes an approach for optimising trade execution in a limit order market. The way a trade is executed becomes important when the trade is a significant proportion of the day's turnover in a particular security. Under these circumstances limited liquidity leads to a significant transaction cost referred to as trade shortfall. We describe a method for calculating a trade execution plan which balances intra-day variations in the supply of liquidity against the risk of adverse future price movements. Our trade execution plans correspond to solutions of discrete time dynamic programming problems. This formulation admits the specification of transaction costs within a Value at Risk framework. The trade execution plans are derived and tested for three popular stocks on the Australian Stock Exchange (ASX). The performance of the plans is evaluated on an out of sample test set of the limit order book for each security and compared to three simpler trade execution strategies.

We investigate the effectiveness of a financial time-series forecasting strategy which exploits the multiresolution property of the wavelet transform. A financial series is decomposed into an over complete, shift invariant scale-related representation. In transform space, each individual wavelet series is modeled by a separate multilayer perceptron (MLP). We apply the Bayesian method of automatic relevance determination to choose short past windows (short-term history) for the inputs to the MLPs at lower scales and long past windows (long-term history) at higher scales. To form the overall forecast, the individual forecasts are then recombined by the linear reconstruction property of the inverse transform with the chosen autocorrelation shell representation, or by another perceptron which learns the weight of each scale in the prediction of the original time series. The forecast results are then passed to a money management system to generate trades.

An analogue VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analogue tech(cid:173) niques were chosen to meet the strict power and area requirements of an Implantable Cardioverter Defibrillator (ICD) system. The ro(cid:173) bustness of the neural network architecture reduces the impact of noise, drift and offsets inherent in analogue approaches. The net(cid:173) work is a 10:6:3 multi-layer percept ron with on chip digital weight storage, a bucket brigade input to feed the Intracardiac Electro(cid:173) gram (ICEG) to the network and has a winner take all circuit at the output. The network was trained in loop and included a commercial ICD in the signal processing path. The system has suc(cid:173) cessfully distinguished arrhythmia for different patients with better than 90% true positive and true negative detections for dangerous rhythms which cannot be detected by present ICDs. The chip was implemented in 1.2um CMOS and consumes less than 200n W max(cid:173) imum average power in an area of 2.2 x 2.2mm2.