Advanced automotive control applications such as steer-by-wire are typically implemented as distributed systems comprising many embedded processors, sensors, and actuators interacting via a communication bus. They have severe cost constraints, but demand a high level of safety and performance. Motivated by the need for timely diagnosis of faulty actuators in such systems, we present a method to achieve distributed failure diagnosis under deadline and resource constraints. Actuators are diagnosed in distributed fashion by processors to provide a global view of their fault status. The integration of software-based tests for actuator diagnosis within the overall control application is studied. These tests are implemented using analytical redundancy and execute concurrently with the control tasks. The test scheduling problem is then formulated and solved to guarantee actuator diagnosis within designer-specified deadlines while meeting control performance goals. As a secondary objective, the scheduling algorithm also reduces the number of processors required for diagnosis. We demonstrate the practicality of the proposed diagnosis approach by applying it to a steer-by-wire example to identify failed actuators in timely fashion.

A control flow fault occurs when a processor fetches and executes an incorrect next instruction. Executable assertions, i.e., special instructions that check some invariant properties of a program, provide a powerful and low-cost method for on-line detection of hardware-induced control flow faults. We propose a technique called ACFC (Assertions for Control Flow Checking) that assigns an execution parity to a basic block, and uses the parity bit to detect faults. Using a graph model of a program, we classify control flow faults into skip, re-execute and multi-path faults. We derive some necessary conditions for these faults to manifest themselves as execution parity errors. To force a control flow fault to excite a parity error, the target program is instrumented with additional instructions. Special assertions are inserted to detect such parity errors. We have a developed a preprocessor that takes a C program as input and inserts ACFC assertions automatically. We have implemented a software-based fault injection tool SFIG which takes advantage of the GNU debugger. Fault injection experiments show that ACFC incurs less performance overhead (around 47%) and memory overhead (around 30%) than previous techniques, with no significant loss in fault coverage.

Advanced automotive control applications such as steer and brake-by-wire are typically implemented as distributed systems comprising many embedded processors, sensors, and actuators interconnected via a communication bus. They have severe cost constraints but demand a high level of safety and performance. Motivated by the need for timely diagnosis of faulty actuators in such systems, we present a general method to implement failure diagnosis under deadline and resource constraints. Actuators are diagnosed in distributed fashion by processors to provide a global view of their fault status. The diagnostic tests are implemented in software using analytical redundancy and execute concurrently with the control tasks. The proposed method solves the test scheduling problem using a static list-based approach which guarantees actuator diagnosis within designer-specified deadlines while meeting control performance goals. As a secondary objective, it also minimizes the number of required processors. We present simulation results evaluating the effectiveness of the proposed method under various design constraints.

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds.

Static off-line scheduling ensures predictability of worst-case behavior and high resource utilization for safety-critical applications but lacks the flexibility needed to deal with run-time fault-tolerance. We present a temporal redundancy-based recovery technique that tolerates transient task failures in statically scheduled distributed embedded systems where tasks have timing, resource, and precedence constraints. Task failures are handled using precomputed contingency schedules that introduce adaptive fault tolerance into table-driven dispatchers. Failures are masked using the spare capacity on the affected processor and the recovery scheme requires no hardware overhead. Our approach combines the benefits of static scheduling with the run-time flexibility needed for fault tolerance in low-cost embedded systems. We present a method to obtain contingency schedules and prove its correctness. We also evaluate the effectiveness of the proposed method through simulation.

We present a new approach for built-in pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the TGC and the CUT; it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds, especially if the test set contains many don't-cares.

We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q/spl Lt/k, a process termed space compaction. The effectiveness of such a compaction method can be measured by its compaction ratio c=k/q. A high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio c/sub max/. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. Given a circuit under test, a fault model, and a test set, we determine q/sub min/, which yields c/sub max/=k/q/sub min/. This provides a fundamental bound on the cost of signature-based BIST. We show that q/sub min//spl les/2 for all the ISCAS 85 benchmark circuits. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS 85 circuits. Finally, we describe multistep compaction, which allows zero aliasing to be achieved with any q, even when q/sub min/>1.

We present a method for designing test generator circuits (TCCs) that incorporate a precomputed test set T/sub D/ in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns T/sub E/ and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing T/sub D/. We show that partially specified test sets, i.e., those that contain a large number of don't-cares, lead to more efficient TGCs. These TGCs are applicable to embedded core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS'85 benchmark circuits and the full-scan versions of the ISCAS'89 benchmark circuits.

We present a method for designing test generator circuits (TGCs) that incorporate a precomputed test set to in the patterns they produce. Our method uses width compression based on the property of d-compatibles, which allows us to encode to more efficiently than previous methods that use only compatibles and inverse compatibles. The TGC consists of a counter, which generates a set of encoded test patterns, and a decompression circuit consisting of simple binary decoders that generate a final sequence containing T/sub D/. These TGCs are applicable to embedded-core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results for the ISCAS 85 and ISCAS CAS 89 benchmark circuits.

Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q/spl Lt/k, a process termed space compaction. The effectiveness of a compaction method can be measured by its compaction ratio c=k/q. However, a high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio c/sub max/. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. For a given circuit tender test, a given fault model, and a given test set, we determine q/sub min/, which yields c/sub max/=k/q/sub min/. This provides a fundamental bound on the cost of signature based BIST. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS-85 benchmark circuits.

Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.

A novel test generation technique for large circuits with high fault coverage requirements is described. The technique is particularly appropriate for circuits designed by silicon compilers. Circuit modules and signals are described at a high descriptive level. Test data for modules are described by predefined stimulus/response packages that are processed symbolically using techniques derived from artificial intelligence. The packages contain sequences of stimulus and response vectors which are propagated as units. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. A prototype test generator which uses the technique to generate tests for acyclic circuits has been implemented. Preliminary results from this program suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible.>

A novel test-generation technique for large circuits with high fault-coverage requirements is described. Circuit modules and signals are represented at a high descriptive level. Test data for modules are represented by predefined stimulus/response packages which are processed symbolically using techniques derived from artificial intelligence. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. Preliminary results from a programmed implementation of the proposed test-generation technique are presented.>