Demo Data from VLDB 2026 / reviewers in the wild / expert
Brian R. Nickerson
dblp:45/6835
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › register allocation
graph coloring register allocation |
0.0 | 1 | 1990 | Graph Coloring Register Allocation for Processors with Multi-Register Operands · PLDI 1990 |
Compilers and program optimization
register allocation |
0.0 | 1 | 1990 | Graph Coloring Register Allocation for Processors with Multi-Register Operands · PLDI 1990 |
Methods — techniques the papers use, named apart from their topics
graph coloring · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | Graph Coloring Register Allocation for Processors with Multi-Register OperandsabstractThough graph coloring algorithms have been shown to work well when applied to register allocation problems, the technique has not been generalized for processor architectures in which some instructions refer to individual operands that are comprised of multiple registers. This paper presents a suitable generalization. Brian R. Nickerson |
PLDI | 1 |