The Unmanned aerial vehicles (UAVs) sector is fast-expanding. Protection of real-time UAV applications against malicious attacks has become an urgent problem that needs to be solved. Denial-of-service (DoS) attack aims to exhaust system resources and cause important tasks to miss deadlines. DoS attack may be one of the common problems of UAV systems, due to its simple implementation. In this paper, we present a software framework that offers DoS attack-resilient control for real-time UAV systems using containers: ContainerDrone. The framework provides defense mechanisms for three critical system resources: CPU, memory, and communication channel. We restrict attacker's access to CPU core set and utilization. Memory bandwidth throttling limits attacker's memory usage. By simulating sensors and drivers in the container, a security monitor constantly checks DoS attacks over communication channels. Upon the detection of a security rule violation, the framework switches to the safety controller to mitigate the attack. We implemented a prototype quadcopter with commercially off-the-shelf (COTS) hardware and open-source software. Our experimental results demonstrated the effectiveness of the proposed framework defending against various DoS attacks.

Directories for cache coherence have been recently shown to be vulnerable to conflict-based side-channel attacks. By forcing directory conflicts, an attacker can evict victim directory entries, which in turn trigger the eviction of victim cache lines from private caches. This evidence strongly suggests that directories need to be redesigned for security. The key to a secure directory is to block interference between processes. Sadly, in an environment with many cores, this is hard or expensive to do.

This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.

This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the single-entry-multiple-data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n3). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13 mum CMOS, the proposed design is synthesized in 1.99 mm2area at 172.4 MHz.

Excessive peak power supply noise (PPSN) causes yield loss problem during test. To reduce PPSN, we proposed a new technique called Capture and Shift Toggle Reduction (CASTR). CASTR performs power reduction during dynamic test compaction so the test length overhead is very small. It also includes pseudo Boolean optimization (PBO) and random-based techniques to improve the results. Experimental results show that we can reduce flip-flop toggles, which is highly correlated with PPSN, by 33.4% during shift mode and 41.2% in capture operation simultaneously for the large ISCAS89 benchmarks.