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Sizheng Wei

dblp:46/1521 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Interconnection networks and networks-on-chip · 60% Parallel and multicore computing · 24% Electronic design automation · 10%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology
hierarchical interconnection network
0.021992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Parallel and multicore computing
multiprocessor system
0.021992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Interconnection networks and networks-on-chip › hypercube network
enhanced hypercube
0.011991
Enhanced Hypercubes · IEEE Trans. Computers 1991
Interconnection networks and networks-on-chip
hypercube network
0.011991
Enhanced Hypercubes · IEEE Trans. Computers 1991
Parallel and multicore computing › parallel architecture
message-passing architecture
0.011991
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Electronic design automation › physical design
routing
0.011991
Enhanced Hypercubes · IEEE Trans. Computers 1991
Interconnection networks and networks-on-chip › switching network › multistage interconnection network
fault-tolerant MIN
0.011988
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network · ISCA 1988
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.011988
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network · ISCA 1988
Performance modeling and evaluation › network performance analysis
network performance modeling
0.011992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Interconnection networks and networks-on-chip
broadcasting
0.011991
Enhanced Hypercubes · IEEE Trans. Computers 1991
Interconnection networks and networks-on-chip
communication locality
0.011991
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Hardware reliability and fault tolerance › network fault tolerance
fault-tolerant network design
0.011988
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network · ISCA 1988

Methods — techniques the papers use, named apart from their topics

unbuffered network model · 0.0design parameter optimization · 0.0buffered network model · 0.0traffic density analysis · 0.0hierarchical network design · 0.0
YearPublicationVenuePosition
1992 Efficient Hierarchical Interconnection for Multiprocessor Systems
abstract
The authors present a novel approach to the design of a class of hierarchical interconnection networks for multiprocessor systems. This approach, based on an architecture providing separate networks for each level, gives a general and flexible way to construct efficient hierarchical networks. The performance and cost-effectiveness of the resulting networks are analyzed and compared in detail, using both unbuffered and buffered network models. It is shown that, if the design parameters are determined based on the degree of locality, the cost-effectiveness of a hierarchical network can be significantly improved. In addition, the authors investigate how to construct a cost-effectiveness hierarchical network by determining appropriate design parameters. Two associated algorithms are developed for this purpose.>
Sizheng Wei, Saul Levy
SC1
1991 Design and analysis of efficient hierarchical interconnection networks
abstract
Hierarchical interconnection networks exploit locality in communication to reduce the number of links in the networks.In this paper, we propose a cla8s of general hierarchical interconnection network8 for message-passing architectures.We show that a new approach to design, choosing the appropriate number of interface nodes, considerably reduces not only intercluster trafic density but also intracluster trafic density.
Sizheng Wei, Saul Levy
SC1
1991 Enhanced Hypercubes
abstract
A hypercube with extra connections added between pairs of nodes through otherwise unused links is investigated. The extra connections are made in a way that maximizes the improvement of the performance measure of interest under various traffic distributions. The resulting hypercube, called the enhanced hypercube, requires a simple routing algorithm and is guaranteed not to create any traffic-congested points or links. The enhanced hypercube achieves noticeable improvement in diameter, mean internode distance, and traffic density, and it also is more cost effective than a regular hypercube. An efficient broadcast algorithm that can considerably speed up the broadcast process in enhanced hypercubes is provided.>
Nian-Feng Tzeng, Sizheng Wei
IEEE Trans. Computers2
1988 Design and Analysis of A Fault-Tolerant Multistage Interconnection Network for Large-Scale Shared Memory Parallel Computers
Gyungho Lee, Sizheng Wei
ICPP (1)2
1988 Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network
abstract
Extra Group Networks, a class of fault-tolerant multistage interconnection networks, are introduced. An EGN-m of size N is designed to have m+1 unique-path multistage-networks of size N/m. This approach of constructing the network allows that an EGN-m can provide full-access capability in the presence of multiple faults, up to m, in any stage. EGNs can also maintain the permutation capability of the unique-path multistage-network of size N in the presence of any single fault. It is shown that EGNs are more cost-effective than other previously proposed fault-tolerant multistage-interconnection networks with a similar fault-tolerant capability.>
Sizheng Wei, Gyungho Lee
ISCA1