With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. We present an accurate technique for modeling and analyzing the effects of parasitic inductance on power grid noise, signal delay and crosstalk. We propose a detailed circuit model composed of interconnect resistance, inductance and distributed capacitance, device decoupling capacitances, quiescent activity in the grid, pad locations, and pad/package inductance which accurately determines current distribution and, hence, on-chip inductive effects, and proves superior to the traditional simplified loop inductance approach. The model uses partial inductances, computed using an analytical formula for a pair of parallel rectangular conductors spaced in any relative position. We present experimental results, obtained from simulations of industrial circuits, that show the importance of various model components while analyzing on-chip inductance. We also propose a simple sparsification technique to handle large, dense partial inductance matrices.

We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power dis?tribution grids. These include an accurate model for the inherent decoupling capacitance of non-switching devices, as well as a sta?tistical switching current model for the switching devices. More?over, three new simulation techniques are presented for problem size-reduction and speed-up. Results of application of these tech?niques on three PowerPCtmmicroprocessors are also presented.