A processor that applies a heterogeneous architecture to the problem of real-time image recognition has been developed. Several unique features distinguish this work from other work in this field and are the subject of this paper. They include the following: (1) use of a complete set of documented applications of automatic target recognition to derive and validate processor requirements; (2) choice of a heterogeneous architecture that integrates several types of processors; (3) development of image-processing-domain custom integrated circuits; (4) application of wafer-scale multichip module miniaturization to the image processing pipeline; and (5) use of a piecewise-connected hierarchy of simulation tools, providing for connectivity of simulation both vertically (i.e., from chip through boards to subsystem) and horizontally (i.e., board vs. multichip module domain). This processor has been programmed with several recognition algorithms and delivered in a baseline 20-stage-pipeline-configuration, where it achieves over 20 billion reduced instruction set (RISC)-equivalent operations/sec upon 16-bit pixels.

This paper presents a new architecture for image processing. It consists of a pipeline of identical programmable serial processing stages, referred to as a cytocomputer. Comparisons are made between cytocomputer and parallel array systems. Cytocomputer systems are shown generally to possess the advantages of lower complexity, high bandwidth and greater architectural flexibility. A first generation system is described and examples of processing are illustrated. Finally, current development efforts are described.