Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic.

This article describes an IBM-developed parallel software methodology called Integrated Manufacturing and Development (IMaD).IMaD is a super-scalable AIX application written in the C programming language and makes use of the Message Passing Interface (MPI).It is built specifically to support Product Engineering (PE) for full-scale integrated circuits (IC), like microprocessors, and encompasses failure, yield, and reliability design and analysis.Because an IC is constructed of smaller building-block circuits, many aspects of its behavior are learned from a local analysis of some subset of the IC.However, there are global aspects of an IC-such as its power-grid electrical distribution that require a full-scale formulation, solution, evaluation, and visualization.This sets the stage for some very large problems that demand enormous computational and memory resources.In answer to these demands, IMaD provides a parallel processing solution that incorporates novel methods of both topographic partitioning of the IC and of solving the global electrical simulation equations.1 This architecture was inspired by Mozumder [5].1

A new methodology is used for the design verification of bipolar array chips. Here the authors apply analog methods to verify the logic function of the chip's basic circuits or macromodels and the noise margins. They also check for reliability by computing the current density at each device contact stud. The logic paths are implicitly verified. Several algorithms are used as building blocks in an implementation program. This includes a recursive scheduling algorithm, a Gray algorithm and an algorithm to treat differential pairs. A nonlinear Gauss-Seidel method for decoupling and solving a nonlinear set of algebraic equations is described.>

HLSIM is an APL hierarchical logic simulator that can deal with nested models. The program has all the facilities to handle large VLSI circuits with complicated sequential logic, including full chip simulation. The authors discuss two major programs: an analog to digital netlist converter and a new digital simulator implemented in APL, a natural environment for logic simulators, especially when its powerful APL nested array facilities are used. The netlist converter takes a hierarchical analog netlist and supplementary files for the leaf models, and creates a digital model of the VLSI circuit. A discussion of the simulator includes its data structure, two algorithms for the static (zero) and the dynamic (unit or variable) delay modes of simulation. The authors also discuss how to handle unique features of the bipolar circuits including emitter, collector dots and differential pairs. Three types of gates can be used: primitive, truth tables, and behavioral models implemented as arbitrary user functions. The last feature enabled them to model and simulate complicated bipolar chips and decoders.>

A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.