This brief presents a wireline transmitter architecture, enabling multilevel signaling with feedforward equalization (FFE) in voltage-mode. A compact R2R-DAC-based front end is proposed and analyzed in terms of its speed, power consumption, and linearity. A voltage-mode PAM-4 transmitter with 2-tap FFE utilizing the proposed architecture is implemented in the 65-nm CMOS technology. It achieves a data rate of 34 Gb/s and an energy efficiency of 2.7 mW/Gb/s.

With the coming era of Big Data, hardware implementation of machine learning has become attractive for many applications, such as real-time object recognition and face recognition. The implementation of machine learning algorithms needs intensive memory access, and SRAM is critical for the overall performance. This paper proposes a new design of high speed SRAM for machine learning purposes. With fast access time (cycle time: 650 ps, access time: 350 ps), low sensitivity to temperature variation and high configurability (less than 10% performance difference between 125_rcw_tt vs 0_rcw_tt), the proposed SRAM is a better candidate for hardware machine learning system than the conventional SRAM. Compared with Samsung HL 152, our design has smaller size (121×43 um2 vs 127×44 um2) with half the number of pins ports (12 vs 25) and higher speed (2.2GHz vs 0.8GHz).

In this paper, we propose a soft-decision-based FEC scheme which is the concatenation of a non-binary LDPC (NB-LDPC) code and hard-decision FEC code having a compatibility with existing OTU-4 frame structure. The proposed concatenated NB-LDPC + RS frame structure is also provided and the entire frame size is 18,368 bytes. The proposed NB-LDPC(2304,2048) code over GF(24) provides a superior performance at the higher BER region and can be concatenated with HD-FEC code. The simulation result shows that the proposed concatenated NB-LDPC(2304,2048) and RS(255,239) FEC can provide a superior NCG performance over 10.3 dB at a post-FEC BER 10−15and over 10.8 dB with enhanced HD-FEC in the outer code. As a result, the proposed NB-LDPC codes are expected to be strong FEC candidates of soft-decision FEC for 100Gb/s optical transmission system.

In this paper, we address the problem of receiving a digitally modulated signal in the presence of another identically modulated co-channel interference (CCI) signal. We propose a joint MLSE algorithm that uses a dynamic channel description (J-MLSE/DCD). This algorithm deals with CCI more effectively while keeping the overall complexity low. Our approach is to adaptively truncate the channels of both the signal and the interference according to their individual power, thereby greatly reducing the complexity. Analytic BER lower bounds for the J-MLSE algorithms in the time-varying specular multipath Rayleigh-fading channels are derived. Simulation results for the GMSK signals used in the GSM system are presented.

In this paper, we address the problem of receiving a digitally modulated signal in the presence of another identically modulated cochannel interfering (CCI) signal. We propose a joint MLSE algorithm that uses a dynamic channel description (J-MLSE/DCD). This algorithm deals with CCI more effectively while keeping the overall complexity low. In the proposed algorithm, we adaptively truncate the channels of both the desired signal and the CCI according to their individual power, thereby greatly reducing the complexity. We also describe the channel by using only a small number of channel parameters to reduce the channel mismatch before the Viterbi algorithm is applied. Analytic bit-error rate (BER) lower bounds for the J-MLSE algorithms in the time-varying specular multipath Rayleigh-fading channels are derived. Simulation results of the GMSK modulated signals used in the GSM system with path delay spread up to three symbols are presented. We find that the proposed algorithm performs significantly better than the spatial-whitened MLSE and is comparable to the high-complexity joint MLSE.