VLDB 2026 Research / reviewers in the wild / expert
Sigal Asaf
dblp:47/1652
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorTheory of computation · 2Artificial intelligence and machine learning · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 72% Processor architecture and microarchitecture · 28% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.1 | 1 | 2007 | A Framework for the Validation of Processor Architecture Compliance · DAC 2007 |
Electronic design automation › hardware verification and test
coverage analysis |
0.0 | 1 | 2004 | Defining coverage views to improve functional coverage analysis · DAC 2004 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2004 | Defining coverage views to improve functional coverage analysis · DAC 2004 |
Electronic design automation › hardware verification and test
coverage-driven verification |
0.0 | 1 | 2004 | Defining coverage views to improve functional coverage analysis · DAC 2004 |
Methods — techniques the papers use, named apart from their topics
model-based test case generator · 0.1flowcharts · 0.1coverage models · 0.1cross-product coverage modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Applying Constraint Programming to Identification and Assignment of Service Professionals
Sigal Asaf, Haggai Eran, Yossi Richter, Daniel P. Connors, Donna L. Gresh, Michael J. Mcinnis |
CP | 1 |
| 2007 | A Framework for the Validation of Processor Architecture ComplianceabstractWe present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing behavior, wrong understanding of a behavior, or confusion with similar behavior described in the architecture or elsewhere. We formally capture the architecture behavior in the form of flowcharts and automatically derive a list of architecture misinterpretations from these flowcharts. These misinterpretations constitute the backbone of coverage models targeted by a suite of tests. The suite is automatically generated by a model-based test case generator. A compliance validation system based on these principles has been developed and used in two actual industrial processes of checking compliance with the PowerPC architecture. Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled |
DAC | 2 |
| 2005 | Solving Constraints on the Invisible Bits of the Intermediate Result for Floating-Point VerificationabstractTest generation for datapath floating-point verification involves targeting intricate corner cases, which can often be solved only through complex constraint solving. In the process of calculating the result, we use an intermediate result whose significand comprises a finite number of bits and a sticky bit that is 0 if and only if the intermediate result is exact. We refer to all the bits beyond those represented in the final result as the invisible bits. We deal with corner cases that can only be defined via constraints on the intermediate result. Our work investigates the following problem: given a floating-point operation, and constraints on the invisible bits and the sticky bit, find two inputs for the operation that yield an intermediate result compatible with the constraints. The paper supplies a deterministic solution for addition and subtraction, and probabilistic solutions for multiplication and division. It also discusses the application of these algorithms to the verification of floating-point implementations. Merav Aharoni, Sigal Asaf, Ron Maharik, Ilan Nehama, Ilya Nikulshin, Abraham Ziv |
IEEE Symposium on Computer Arithmetic | 2 |
| 2004 | Defining coverage views to improve functional coverage analysisabstractCoverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimidating and time-consuming task. Practically, it can only be done by focusing on specific parts of the model. This paper presents a method for defining views onto the coverage data of cross-product functional coverage models. The proposed method allows users to focus on certain aspects of the coverage data to extract relevant, useful information, thereby improving the quality of the coverage analysis. A number of examples are provided that show how the proposed method improved the verification of actual designs. Sigal Asaf, Eitan Marcus, Avi Ziv |
DAC | 1 |
| 2003 | Solving Range Constraints for Binary Floating-Point InstructionsabstractWe present algorithms that solve the following problem: given three ranges of floating-point numbers R/sub x/, R/sub y/, R/sub z/, a floating-point operation (op), and a rounding-mode (round), generate three floating-point numbers x~, y~, z~ such that x~/spl isin/R/sub x/, y~/spl isin/R/sub y/, z~/spl isin/R/sub z/ and z~=round(x~ op y~). This problem, although quite simple when dealing with intervals of real numbers, is much more complex when considering ranges of machine numbers. We provide full solutions for add and subtract, and partial solutions for multiply and divide. We use range constraints on the input operands and on the result operand of floating-point instructions to target corner cases when generating test cases for use in verification of floating-point hardware. The algorithms have been implemented in a floating-point test-generator and are currently being used to verify floating-point units of several processors. Avi Ziv, Merav Aharoni, Sigal Asaf |
IEEE Symposium on Computer Arithmetic | 3 |