Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Level Design flow for asynchronous circuits based on Register Transfer Level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles.

A fault model for programmable logic arrays (PLAs) is discussed. This model maps realistic failures on four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that multiple stuck-at faults are equivalent to multiple crosspoint faults, multiple bridging faults are sub-equivalent to multiple crosspoint faults, and the set of patterns detecting multiple crosspoint faults is a subset of the set of patterns detecting multiple bridging faults. Hence, the set of patterns detecting multiple crosspoint faults also detects all multiple stuck-at faults and multiple bridging faults. This reduces the fault model for PLAs to two classes: multiple missing/extra crosspoint faults and multiple breaks.>

A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect to multiple stuck-at faults and multiple missing/extra crosspoint faults.