Security is critical for wireless sensor networks (WSN)deployed in hostile environments since many types of attacks could reduce the trust on the global functioning of any WSN. Many solutions have been proposed to secure communications for WSNs and most of them rely on a centralized component which behaves as a certificate authority. We propose in this paper a distributed solution able to ensure authentication of nodes at any time without having any on-line access to a certificate authority. Each node will be equipped with a Trusted Platform Module (TPM) which is able to store keys with security. Each node will have its own public key and private key pair in the TPM and a certificate of the public key. The certificate is issued off-line when setting-up the node. When a node communicates with another, it has to sign the message with its own private key (done securely by the TPM) and sends the message, the signature and the certificate of the public key. The evaluation of the solution has been done using simulation and the overhead added by integrating authentication does not exceed 15% of energy consumption.

This paper presents an artificial noise strategy to increase physical-layer security in Cognitive Wireless Sensor Networks (CWSN). Spectrum sensing, information sharing and collaborative cognitive features are used to avoid eavesdropping attacks. Artificial noise generation is proposed to conceal the secret message to be transmitted. One important design parameter, the ratio of power allocated to the information bearing signal versus the artificial noise Φ is defined. A simulation framework has been used to simulate different scenarios. The simulations results show that there is a near-optimal Φ value, from 0.8 until 0.96 depending on the number of collaborator nodes, increasing with the number of relay nodes in the network. Also, the simulations show that the more nodes used for the collaboration strategy the less noise per signal is needed for the same Secrecy Outage Probability. As a result, the artificial noise strategy is seen to be highly effective for increasing the secrecy in CWSN.

Traditional approaches for fixed-point characterization are based on long simulations or additive noise models that do not show the nonlinear behavior of the quantization operations in reasonable time. In this paper, a novel interval-based approach that provides both tighter and faster results than the existing approaches is presented. It is based on a nonlinear adaptation of the quantization operations of affine arithmetic (AA). The results obtained with this method are compared to other published interval-based approaches, and the problem of interval oversizing is discussed in detail. Simulations show that: 1) the propagation techniques are not well suited to characterize the quantized linear systems with feedback loops; 2) the AA provides oversized bounds in this type of systems; and 3) the proposed adaptation does not provide guaranteed bounds as in the traditional interval-based computations, but it provides tighter estimates of the evolution in time of the ranges of the fixed-point signals and better runtime than the existing interval-based characterization techniques.

In this paper we address the high-level synthesis of multiple word-length DSP algorithms over programmable devices (FPGAs). Previous approaches tend to simplify the set of resources, thus alleviating the complexity of the high-level synthesis, but leading to non-optimal solutions. Here, we present a high-level synthesis framework that overcomes these limitations by means of considering: (i) both logic-based and embedded multipliers, (ii) both constant and generic multipliers and (iii) variable latency resources. A simulated annealing based approach for the combined scheduling, resource allocation and binding tasks is presented. When compared to previous approaches, area improvements of up to 60% are reported

Hardware implementation of arithmetic modules is a time-consuming task. Consequently, there is a demand for CAD tools that help the designer in reducing design times. This paper presents a floating-point module generator that allows user specification of the mantissa, exponent bit-width and clock period. This tool generates synthesizable VHDL code in a readable format that can be modified by the designer. It also optimizes circuit performance, providing modules with high-speed execution times, that are comparable to those of existing specific implementations.

One of the main challenges in bioinformatics nowadays is to create a framework to compare efficiently new DNA sequence information to large existing databases. Optimal methods, such as the Smith-Waterman algorithm, provides more sensitive results than heuristic algorithms such as FASTA and BLAST, with the drawback of increased computational complexity. FPGAs implementations of Smith-Waterman exploit the intrinsic parallelism in the algorithm and achieve computation time reductions of several orders of magnitude. In this paper we present an implementation of a Smith-Waterman linear systolic array that doubles throughput of existing ones with a minimum increase of area. The processing speed improvement is achieved by means of assigning the computation of four edit distances to a single systolic cell. Implementation results on Xilinx devices XC2V6000 and XCV1000E are reported. An array that processes 8000-nucleotid DNA sequences achieves 3200 BCUPS operating at 200 Mhz on a XC2V6000-5 device.

This work describes a domotic system (VESTA) oriented to low to medium rate domotic wireless applications, multi-interface communication gateway, low power and low cost, open code based software, micro Web server implemented and with distributed intelligence between its two types of components: the processing platform, Antares and the remote modules, Mercurios. Antares and Mercurio can be mixed in any number and can interface with each other as well as with commercial and non commercial devices. Antares is the processing platform built around a Motorola Coldfire processor with an embedded /spl mu/CLinux operating system. Mercurio is a low power battery operated radio modem that includes an 8051 microcontroller for dynamic networking operations. The applicability of the platform is demonstrated through three application cases: a system to reduce energy consumption in hotels funded by the Islas Baleares Government (Spain), an automatic nursing system for Alzheimer patients and a fertirrigation and climate control for greenhouses and extensive farming systems funded by Spanish agricultural associations.