An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high-resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single-bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-μm CMOS technology, chip area of the proposed ADC is 1310 × 125 μm2. Operating at 1.8 V supply, the ADC consumes 160-426 μW for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.

High Temperature Superconducting (HTS) power cables are being developed for specific low and medium voltage applications that need to support large and variable load currents. Developments of HTS cables for electric ship applications with integrated medium voltage direct current (MVDC) power systems are discussed. The electrical and cryogenic thermal design challenges and the potential solutions for HTS power cables are discussed. This paper includes a section about recent developments in helium gas cooled HTS cable designs in terms of gaseous media and dielectric strength as well as new cable design options.

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.

Capacitive non-contact electric field sensing is a prime modality for signal detection and communication in a variety of contexts ranging from bio-potential measurements and proximity sensing to body centered communication and human computer interaction. Although recent developments in the space of wearable sensors have greatly expanded the sensory capability, they simultaneously place more stringent requirements on the front-end. Thus, low-noise power efficient front-ends that can demonstrate low input parasitic capacitances can accelerate the adoption of sensing and communication technologies that exploit this form of capacitive coupling. To this end, we present results from a 193μm2, 6μW/MHz, unity-gain, charge buffer, fabricated in 65nm CMOS for use in electric field sensing.

Recent advances in DNA sequencing technology have enabled Next Generation Sequencing (NGS) instruments to accelerate generating billions of DNA reads in a few days. However, the management of enormous NGS data and the concurrent analysis of these vast amount of data requires a great deal of computing power and memory as well as huge disk storage. Current popular job scheduling systems provide efficient ways for managing and scheduling vast amount of analysis based on the available computing resources but don't consider the maximum amount of Input/Output (I/O). Thus, when executing large number of genome analysis on a large scale cluster system, the maximum bandwidth of storage I/O is insufficient to utilize all computing resources so the analysis jobs are frequently suspended. Here we developed a disk I/O aware job submission scheduler to maximize disk I/O usage but not hampering previously running jobs due to the heavy disk I/O of a new job. And we constructed a cancer genome analysis pipeline by using our I/O aware scheduler and HPC resources in National Institute of Supercomputing and Networking (NISN) to overcome the obstacles of concurrent analysis for vast amount of NGS data. Based on our I/O aware job submission scheduler, we performed major genome analyses on over 50 case-control pairs of chromophobe renal cell carcinoma patients whole genome samples sequenced by The Cancer Genome Atlas (TCGA) and successfully completed all analysis jobs while maintaining no jobs to be suspended by I/O bottleneck.

Since Nagoya protocol is entering into force, it has become very important issue to find alternative herb with similar efficacy. To find out alternative herbs, we adopted MeSH which contains semantic information derived from papers in the MEDLINE database which covers the medical, pharmaceutical, and biological worldwide research. Among 16 categories of MeSH, we chose 3 categories which are related to herbal efficacy. And we surveyed the advanced research addressing the MeSH semantic measure and selected the most accurate measure which is validated from the research. And we designed the algorithm which is composed of three steps; first we build corpus using MeSH tags of papers which are dealing with 4176 species of native Korean plants. Second we search papers of target herb and native plants respectively using scientific names and extract MeSH tags in it. Third we calculate the similarity between target herb and each native plant using MeSH similarity. In this paper, we proposed the algorithm to find out the herbs with similar efficacy. Now we are under implementation of the algorithm and are going to do in vitro experiments to measure the accuracy of algorithm.

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.

Abstract Summary: We are constructing an ontology for traditional Korean medicine, and we started with medicinal materials to express the relationships between patients' symptoms, diseases and treatments. Biological materials and mineral resources have been used traditionally for patient treatments. The ontology includes various data related to these materials, such as their scientific names, parts of materials used, effectiveness and related oriental organ of the human body. Availability: http://tkm.kiom.re.kr/ontology/TraditionalKoreanMedicine.rdf-xml.owl (10–20 s using Internet Explorer.) Contact: [email protected] Supplementary information: Supplementary data are available at Bioinformatics online.

The Ministry of Education and Human Resources Department of Korea have formulated various policy for development of teacher's ICT competence. But most of efforts expended upon ICT utilization currently, emphasize the ability which can handle computer skillfully than the ability for practical use in instruction, so that cannot induce distinct competence according to the duties and operations of teachers. The teachers' ICT certification system in sixteen cities and provinces evaluates only simple computer skills, overlooking educational activities that are main tasks of teachers. Therefore, this study developed self-assessment tools for web-based teachers' ICT use and investigated ICT utilization, targeting teachers from sixteen Korean cities and provinces.

This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next generation computing system and describes the HW/SW codesign and verification methodology using SystemC.

One of the changes that the "information age" has brought to classrooms is that a web-based classroom management support system (WBC) is now required for more efficient classroom management in elementary schools. This research aims at finding desirable Internet uses for more efficient classroom management through designing and implementing a web-based classroom support system. It has been possible to support classroom management beyond the limits of time and space with content found on the web and through guiding learners' internet usage in educational directions utilizing the resources on the web in more academic ways, and developing each learners' own special abilities and aptitudes. A WBC system is expected to offer upgraded classroom management when applied in classrooms to help direct learners' active participation.

In this paper, we present a test structure for identifying faulty processing or switching nodes in massively parallel processing systems. The structure does not require any precomputed and stored responses. It is based on group probing and leads to a high test performance by exploiting parallelism in testing. Once a fault is detected, the expected response is obtained by finding a dominant group of nodes producing an identical response. The response from the dominant group is then broadcast to all the nodes under test to determine their fault status by a local comparison. The technique can be used to test identical chips or processing nodes regardless of how the test vectors are generated.

In a board level design with boundary scans, each chip on a board can be tested by loading test vectors and collecting responses through a boundary scan chain. Since the boundary scan may serialize the test process, the overall test time can be reduced if multiple boundary scan chains are used. In that case the test time depends on how the boundary scan chips are connected into multiple chains. In this paper, we present a technique for configuring multiple boundary scan chains to minimize the test time for boundary scan chips on a board.

The paper presents a survey of test sequence generation methods for testing the conformance of a protocol implementation to its specification which is modeled as a finite state machine (FSM). The past decade (1984-94) has been a period of intense research in test sequence generation, since it is one of the most important issues in the area of protocol conformance testing. There have been four major methods of conformance test generation reported in the literature: transition tours, distinguishing sequences, characterizing sequences, and unique input/output sequences. These methods are used to test the control portion of a protocol specification. Applications of these methods to the finite state machine model are discussed and then comparison and analysis are made in terms of two criteria: fault coverage and test sequence length. Also, some issues which are related to test generation for protocol conformance testing are identified.>