We introduce a rapid measurement-based traffic modeling technique that can be completely automated; no parameter tuning or other manual intervention is required. The model is designed such that both its rate cumulative density and power spectral density functions match those of the original traffic over the time-scales of interest. Since the model is derived from Fourier series representation and the discrete-time Markov Modulated Poisson Process (MMPP), it can easily capture diverse, even non-rational, power spectral densities.

This paper evaluates the buffer requirements resulting from rate mismatch in a 32/spl times/32 ATM switch with sixty OC-3 (155 Mbps) and four T-1 (1.5 Mbps) ports. Rate mismatch is expected to be a common occurrence in ATM wide area networks, particularly at the network seams. Without proper dimensioning, the switch buffers can rapidly overflow as a result of high-speed input traffic destined to a low-speed port. We specifically consider the Cisco Systems LightStream 1010 ATM switch architecture in our analysis, and compare the design options of a larger common shared buffer with that of adding buffers to each T-1 output port. We consider traffic from individual high-speed servers, LAN workstations, and aggregated Ethernet traffic.

This paper evaluates the additional buffer requirements of an ATM shared-memory switch using packet-level (store-and-forward) rather than cell-level (cut-through) service scheduling. Packet-level scheduling is important to tag and IP switching for multipoint-to-one services; it allows different connections to be merged into a single virtual connection to reduce routing complexity. Cisco Systems will incorporate packet-level scheduling in their LightStream 1010 ATM switch using a feature upgrade card possessing per flow queueing; we thus specifically consider the LightStream 1010 architecture in our analysis.

We develop analytical approximations for the first order and second-order statistics of the delay jitter experienced by a stationary traffic stream multiplexed at a major communication node; these approximations are then used to gain insight into the behavior of jitter at a single node under diverse system and traffic conditions. Our construction applies when the node can be modeled as a finite quasi-birth-death (QBD) process and the interarrival time probability density functions (pdfs) for the tagged stream are obtainable. We compare the jitter performance of three different tagged streams: periodic, Poisson, and on/off binary Markov process. Because jitter behavior is most deleterious for the former, we study the individual effects of various system and traffic parameters on the jitter statistics of a periodic stream multiplexed in a Markov-modulated Poisson process (MMPP)/M/1/K system. To demonstrate the flexibility of this analytical technique, we also consider a JPEG video stream multiplexed with JPEG, MPEG, and data sources on an OC-12 line.

We propose an explicit-rate ABR feedback control scheme, UT (uniform tracking). The distinct feature of UT is that it achieves max-min fairness by tracking an effective number of sources; specific constraint information is not required. As a result, its implementation is much simpler than that of other fair control schemes; indeed, its complexity is similar to that of unfair explicit-rate controls. In the thorough simulation study, UT demonstrates its ability to scale with speed, distance, number of users (both persistent and bursty), and number of switches while remaining robust, efficient, and fair under stressing conditions with MPEG background traffic and multiple propagation delay loops.

This paper uses measurement-based traffic models to evaluate a shared-memory ATM switch with 32/spl times/32 155 Mbit/s ports and an external multicasting engine; this is the design of Cisco System's next-generation ATM switch, the LightStream-1010 (LS-1010). Assuming that the multicast traffic can take approximately 30% of the total switch load, we find that an external multicasting engine requires a 32 (8) cell buffer at a replication rate of 16 (64) cells per cell service time. We discover that in a multimedia environment, the shared-memory architecture requires 10-30 times less total memory than the bus architecture; a 64 K cell buffer is sufficient to handle 90% utilization with the nonuniform traffic that we investigated. Multiple-priority classes are considered.