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A. Salz

dblp:47/4934 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.011989
IRSIM: An Incremental MOS Switch-Level Simulator · DAC 1989
Electronic design automation
hardware verification and test
0.011989
IRSIM: An Incremental MOS Switch-Level Simulator · DAC 1989
Electronic design automation › circuit simulation
incremental simulation
0.011989
IRSIM: An Incremental MOS Switch-Level Simulator · DAC 1989
Electronic design automation › circuit simulation
switch-level simulation
0.011989
IRSIM: An Incremental MOS Switch-Level Simulator · DAC 1989
YearPublicationVenuePosition
1989 IRSIM: An Incremental MOS Switch-Level Simulator
abstract
This paper describes IRSIM, an incremental switch-level simulator for MOS transistor circuits. In IRSIM, the circuit under simulation can be modified and then incrementally resimulated. This allows error correction and circuit operation verification to be performed in time proportional to the size of the modifications rather than the size of the entire circuit. To accomplish this incremental simulation, IRSIM maintains a history of circuit activity during simulation and only resimulates the sections of the circuit that deviate from their history. The program was tested on several corrections to errors that actually occurred in the design of a VLSI microprocessor. These errors were corrected and the circuit was incrementally resimulated 1.6 to 3500 times faster than simulating the entire circuit.
A. Salz, Mark Horowitz
DAC1