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Giorgos Manetas

dblp:47/5274 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.112006
An automated and efficient substrate noise analysis tool · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
physical design		 0.112006
An automated and efficient substrate noise analysis tool · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › circuit modeling
substrate coupling modeling		 0.112006
An automated and efficient substrate noise analysis tool · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › signal integrity
substrate noise analysis		 0.112006
An automated and efficient substrate noise analysis tool · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

surface impedance matrix · 0.1green's function · 0.1boundary element method · 0.1
YearPublicationVenuePosition
2006 An automated and efficient substrate noise analysis tool
abstract
This paper presents a methodology for the efficient modeling of substrate noise coupling. A closed-form Green's function for nonuniformly doped substrates is employed with the correct singular characteristics. A novel global surface impedance matrix scheme is introduced to efficiently model nonuniformly doped wells, channel stop implants, and buried layers. Layout, device, and netlist extractors are developed so as to integrate our boundary element method (BEM) solver with commercial layout and circuit simulation tools.
Cole E. Zemke, Giorgos Manetas, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3